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Metal–insulator–metal micro-capacitors for integrated energy storage up to 105 Hz

Autor: E Hourdakis, M A Botzakaki, N J Xanthopoulos

Publikováno v: Journal of Physics D: Applied Physics. 55:455502

Metal–insulator–metal (MIM) micro-capacitors for use in integrated energy storage applications are presented. A new, simple and batch Si processing compatible method for the creation of high aspect ratio metallic 3D structures on the surface of a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::36b91fbe8f2fa03fb28f1d466e94c4cd
https://doi.org/10.1088/1361-6463/ac914a

Three-dimensional vertical Si nanowire MOS capacitor model structure for the study of electrical versus geometrical Si nanowire characteristics

Autor: A.G. Nassiopoulou, Guilhem Larrieu, Adrien Casanova, E. Hourdakis

Publikováno v: Solid-State Electronics
Solid-State Electronics, Elsevier, 2018, 143, pp.77-82. ⟨10.1016/j.sse.2017.11.003⟩
Solid-State Electronics, 2018, 143, pp.77-82. ⟨10.1016/j.sse.2017.11.003⟩

International audience; Three-dimensional (3D) Si surface nanostructuring is interesting towards increasing the capacitance density of a metal-oxidesemiconductor (MOS) capacitor, while keeping reduced footprint for miniaturization. Si nanowires (SiNW

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ee6f075268bbe8d65d23820313a7a28
https://doi.org/10.1016/j.sse.2017.11.003

Simple method for determining Si p-n junction depth using anodization

Autor: Androula G. Nassiopoulou, Mario Barozzi, E. Hourdakis, G. Pepponi

Publikováno v: Microelectronic Engineering. :111558

A simple method for the determination of a Si p+/n junction depth is presented. The method is designed to delineate the specific junction due to its importance in the field of Si solar cells where cost effective and fast characterization techniques a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::670f402dc771d0509f7818a1eb0d5251
https://doi.org/10.1016/j.mee.2021.111558

Model 3D MOS capacitor system using regular arrays of vertical Si nanowires

Autor: Adrien Casanova, A.G. Nassiopoulou, Guilhem Larrieu, E. Hourdakis

Publikováno v: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

A model system of three-dimensional (3D) Si nanowire (SiNW) Metal-Insulator-Semiconductor (MIS) capacitor arrays with vertical Si nanowires of diameter 430 nm and height 1.35 and 2.5 µm respectively has been fabricated and studied. The gate dielectr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::71960234cc4a81dee5d15523c1c1818b
https://doi.org/10.1109/ulis.2017.7962618