Zobrazeno 1 - 10
of 46
pro vyhledávání: '"E, Herruzo"'
Publikováno v:
Proceedings of the Smart City Summit Demos 2018, Guimaraes, Portugal, 21.-23. November 2018.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca4f7a769bee4a8cfa1fa70d589b963d
https://doi.org/10.4108/eai.21-11-2018.2280406
https://doi.org/10.4108/eai.21-11-2018.2280406
Akademický článek
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Publikováno v:
2018 XIII Technologies Applied to Electronics Teaching Conference (TAEE).
As it is well known, teaching simulators are very useful resources to teach the practices of the subjects and that students understand in a more optimal way the theoretical concepts taught. Specifically, this work presents a teaching simulator, SICOM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78dee1c3ba5e3ef28ec14033729e369f
https://doi.org/10.1109/taee.2018.8476041
https://doi.org/10.1109/taee.2018.8476041
Publikováno v:
IEEE Transactions on Education. 51:336-341
This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e7258adcf0392283ad9e06d5fbe793d
https://doi.org/10.1109/te.2008.916767
https://doi.org/10.1109/te.2008.916767
Autor:
F.J. Quiles Latorre, E. Herruzo Gomez, A. D. Santana Gil, M. Hernandez Calvino, J. I. Benavides Benitez
Publikováno v:
ReConFig
The microprocessor performance is highly dependent on cache size and structure. This work presents a new design of a reconfigurable cache implemented on FPGA and based on a previous work. Advantages of the new design and the important enhancements ar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff0e5276157fc8fb809b783124835af9
https://doi.org/10.1109/reconfig.2012.6416768
https://doi.org/10.1109/reconfig.2012.6416768
Publikováno v:
ReConFig
Cache memory is a common structure in computer system and has an important role in microprocessor performance. A relationship between the performance of particular algorithm and main cache parameters such as associativity, number of words per block a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4f6bb0b6b86867cd9da50e3fac9161c
https://doi.org/10.1109/reconfig.2010.26
https://doi.org/10.1109/reconfig.2010.26
Publikováno v:
CLEI Electronic Journal 12 (1, 5) (2009)
Helvia. Repositorio Institucional de la Universidad de Córdoba
instname
CLEI Electronic Journal, Vol 12, Iss 1 (2009)
Helvia. Repositorio Institucional de la Universidad de Córdoba
instname
CLEI Electronic Journal, Vol 12, Iss 1 (2009)
Nowadays, the computational systems (multi and uniprocessors) need to avoid the cache coherence problem. There are some techniques to solve this problem. The MESI cache coherence protocol is one of them. This paper presents a simulator of the MESI pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e7b1515f31d96a79fc7e4f53ee5bb017
https://hdl.handle.net/10396/11468
https://hdl.handle.net/10396/11468
Publikováno v:
Computational Science – ICCS 2008 ISBN: 9783540693833
ICCS (1)
ICCS (1)
Program locality exploitation is a key issue to reduce the execution time of scientific applications, so as many techniques have been designed for locality optimization. This paper presents new compiler algorithms based on array padding that optimize
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ecea6e09e6fb31d0633fc390433ec848
https://doi.org/10.1007/978-3-540-69384-0_91
https://doi.org/10.1007/978-3-540-69384-0_91
Publikováno v:
ICSAMOS
The paper describes a framework for analyzing the cache content on affine references to arrays in loops. The framework is based on a small set of key cache parameters. We study the relation between these cache parameters and the data memory layout of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::914e5a52288cab19a1e15d5f5c7d460c
https://doi.org/10.1109/icsamos.2007.4285749
https://doi.org/10.1109/icsamos.2007.4285749
Publikováno v:
MSE
This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the ISA level. The tool was developed through a series of laboratory exercises in computer architecture. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d041ef872536cb365194e5e38269ae59
https://doi.org/10.1109/mse.2007.74
https://doi.org/10.1109/mse.2007.74