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2020 IEEE International Solid-State Circuits Conference-(ISSCC), Feb 2020, San Francisco, United States. pp.46-48, ⟨10.1109/ISSCC19947.2020.9062927⟩

International audience; In the context of high performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for AI application is raising more and more challenges. Due to the increasing costs of a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::08df86ec2b2f65ac2fd786245b437f01
https://hal.archives-ouvertes.fr/hal-02985945

Technologies et tendances. (French)

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Publikováno v: Clefs CEA (English); Nov2021, p29-32, 4p

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A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.

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Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip.

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Publikováno v: 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE); 01/01/2014, p1-4, 4p