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This paper presents a high level DSP architecture compiler for cycle-constrained filters and datapath applications. The tool offers an easy way to get, from an equation representation of a filter, a synthetisable VHLD description of an application sp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______805::fac833cf436c84c1d4cc5cfb53ca8c81
http://doc.rero.ch/record/6676/files/Drollinger_Andreas_-_ASIC_DSP_compiler_for_optimized_synthesis_20070419.pdf
http://doc.rero.ch/record/6676/files/Drollinger_Andreas_-_ASIC_DSP_compiler_for_optimized_synthesis_20070419.pdf
Autor:
Drollinger, Andreas, Pellandim, Fausto
Publikováno v:
Electronic Engineering Times (01921541). 11/06/2000, Issue 1139, p78. 2p. 1 Diagram.
