Zobrazeno 1 - 10
of 1 003
pro vyhledávání: '"Drechsler, Rolf"'
Functional simulation is an essential step in digital hardware design. Recently, there has been a growing interest in leveraging Large Language Models (LLMs) for hardware testbench generation tasks. However, the inherent instability associated with L
Externí odkaz:
http://arxiv.org/abs/2411.08510
The use of Boolean Satisfiability (SAT) solver for hardware verification incurs exponential run-time in several instances. In this work we have proposed an efficient quantum SAT (qSAT) solver for equivalence checking of Boolean circuits employing Gro
Externí odkaz:
http://arxiv.org/abs/2409.03917
As AI solutions enter safety-critical products, the explainability and interpretability of solutions generated by AI products become increasingly important. In the long term, such explanations are the key to gaining users' acceptance of AI-based syst
Externí odkaz:
http://arxiv.org/abs/2408.16780
In digital circuit design, testbenches constitute the cornerstone of simulation-based hardware verification. Traditional methodologies for testbench generation during simulation-based hardware verification still remain partially manual, resulting in
Externí odkaz:
http://arxiv.org/abs/2407.03891
Autor:
Singh, Simranjeet, Bende, Ankit, Jha, Chandan Kumar, Rana, Vikas, Drechsler, Rolf, Patkar, Sachin, Merchant, Farhad
In-memory computing (IMC) has gained significant attention recently as it attempts to reduce the impact of memory bottlenecks. Numerous schemes for digital IMC are presented in the literature, focusing on logic operations. Often, an application's des
Externí odkaz:
http://arxiv.org/abs/2407.02921
BinSym is a framework for symbolic program analysis of software in binary form. Contrary to prior work, it operates directly on binary code instructions and does not require lifting them to an intermediate representation (IR). This is achieved by for
Externí odkaz:
http://arxiv.org/abs/2404.04132
Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, between the VP and the HW still exists a gap, as the step from an architectural level VP implementation on the
Externí odkaz:
http://arxiv.org/abs/2311.00442