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pro vyhledávání: '"Dr. V. Sudheer Raja"'
In this paper, a new technique of power reduction in CMOS domino logic is proposed. The proposed technique uses clock gating as well as output hold circuitry. Clock is passed to the domino logic only during the active state of the circuit. During sta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4bac7eb4b122f2febb537840fc1c38a7