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An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______2659::7ac2a9c43a7403131e66d7ec01eefd20
https://zenodo.org/record/8171328
https://zenodo.org/record/8171328
