A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.

Autor: Hoya, K., Takashima, D., Shiratake, S., Ogiwara, R., Miyakawa, T., Shiga, H., Doumae, S.M., Ohtsuki, S., Kumura, Y., Shuto, S., Ozaki, T., Yamakawa, K., Kunishima, I., Nitayama, A., Fujii, S.

Publikováno v: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers; 2006, p459-466, 8p

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.

Autor: Ogiwara, R., Tanaka, S., Itoh, Y., Miyakawa, T., Takeuchi, Y., Doumae, S.M., Takenaka, H., Kunishima, I., Shuto, S., Hidaka, O., Ohtsuki, S.

Publikováno v: IEEE Journal of Solid-State Circuits; Apr2000, Vol. 35 Issue 4, p545-551, 7p

A 0.5 /spl mu/m 3 V 1T1C 1 Mb FRAM with a variable reference bitline voltage scheme using a fatigue-free reference capacitor.

Autor: Miyakawa, T., Tanaka, S., Itoh, Y., Takeuchi, Y., Ogiwara, R., Doumae, S.M., Takenakal, H., Kunishima, I., Shuto, S., Hidaka, O., Ohtsuki, S., Tanaka, S.-I.

Publikováno v: 1999 IEEE International Solid-State Circuits Conference Digest of Technical Papers ISSCC First Edition (Cat No99CH36278); 1999, p104-105, 2p