Zobrazeno 1 - 10
of 54
pro vyhledávání: '"Douglas Yu"'
Autor:
Wen-Chih Chiou, Calvin Lu, Douglas Yu, C.H. Tsai, Christine Chiu, C. T. Wang, P. K. Huang, Kai-Yuan Ting, Shang-Yun Hou, W. H. Wei, Clark Hu
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate m
Autor:
Douglas Yu, Kai-Yuan Ting, Shang-Yun Hou, C. C. Lin, Wen-Chih Chiou, C.H. Tsai, Feng Wei Kuo, C. T. Wang, H. Hsia
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
One of the prominent challenges for widespread adoption of silicon photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
The continuous pursuit of higher compute power with insatiable data bandwidth to meet relentless AI system demands from cloud computing, data centers, enterprise servers, supercomputers, network system and edge computing, has urged new system integra
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
An Innovative SoIS (System on Integrated Substrate) technology is proposed to satisfy higher performance applications cost effectively. SoIS technology leverages wafer process and new materials. This innovative integrated substrate presented signific
Autor:
Chen Chih-Lin, Cheng Yun-Wei, K.-J. Chen, Douglas Yu, C.H. Tsai, Tsung-Ching Huang, M. F. Chen, C. T. Wang, F. Lee, J. Yuan
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
An ultrahigh density 3D technology, SoIC_UHD, with sub-micron pitch inter-chip vertical interconnect enabling a density ≥ 1.2 million bonds/mm2 is reported for the first time. Proven yield and reliability of SoIC_UHD are demonstrated with a foundry
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Inter-chip interconnect pitch miniaturization has become an essential part to enhance die-die communication bandwidth (BW) performance in advanced packaging technology. Among different inter-chip interconnect approaches reported [1]-[9], a fan-out te
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
Immersion in Memory Compute (ImMC) technology with multiple chips and functions in multi-layer stacking integrated using System on Integrated Chips (SoIC™) technology is presented. The technology provides multiple compute and memory chips to interc
Autor:
E. B. Liao, Clark Hu, M. F. Chen, Douglas Yu, C. S. Lin, W. C. Chiou, C. C. Kuo, C.H. Tsai, C. T. Wang
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
A low-temperature System-on-Integrated- Chip (LT-SoIC) technology has been successfully applied to multi-layer 3D memory cube integration, which enables high bandwidth, low power and small footprint memory for future HPC applications. In addition, us
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
A low temperature system-on-integrated-chip (SoIC) bonding and stacking technology is proposed and implemented for 3-D memory integration, such as 3-D static random access memory (SRAM) or dynamic random access memory (DRAM) cube. It extends not only