Zobrazeno 1 - 10
of 87
pro vyhledávání: '"Double patterning lithography"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1381-1394
As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39acbf780f67fe4b2e65c1b4e8a764d8
https://doi.org/10.1109/tcad.2016.2622625
https://doi.org/10.1109/tcad.2016.2622625
Publikováno v:
ASICON
Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24d7c774e792ead17d807e7abb6266a2
https://doi.org/10.1109/asicon47005.2019.8983474
https://doi.org/10.1109/asicon47005.2019.8983474
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 21:1-25
In this article we present a pairwise coloring (PWC) approach to tackle the layout decomposition problem for triple patterning lithography (TPL). The main idea is to reduce the problem to a set of bi-coloring problems. The overall solution is refined
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a01d6c69be7f5ae29a3d88ca0aa5f0b
https://doi.org/10.1145/2764904
https://doi.org/10.1145/2764904
Publikováno v:
ISCAS
In contrast to other studies in IC supply chain security where foundries are classified as either untrusted or trusted, a more realistic threat model is that the foundries are legally and economically obliged to perform trustworthy service, and it is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96e78ff5fa0fc6a0ed8927e22c3f5482
https://doi.org/10.1109/iscas.2017.8050884
https://doi.org/10.1109/iscas.2017.8050884
Publikováno v:
ECS Transactions. 60:173-178
Double patterning using 193 nm immersion lithography has been adapted as the solution to enable 20 nm technology nodes. In the Back end, Litho Etch Litho Etch (LELE) is considered as the most suitable process for this technology. The overlay control
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::042acd71c8031f30b401a22f30bd4d9c
https://doi.org/10.1149/06001.0173ecst
https://doi.org/10.1149/06001.0173ecst
Publikováno v:
Journal of Computational and Theoretical Nanoscience. 10:616-619
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7005a2c5c10d2206a0d6ecc80c6c8c97
https://doi.org/10.1166/jctn.2013.2743
https://doi.org/10.1166/jctn.2013.2743
Publikováno v:
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
We present an efficient layout decomposition flow and the corresponding optimization algorithms to minimize the stitches for double patterning lithography. Also the given power/ground preprocessing method for the flow reduces the complexity, and impr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e7f1a281dea5a42d92691c3b6cc7d80
https://doi.org/10.1109/icsict.2016.7998887
https://doi.org/10.1109/icsict.2016.7998887
Publikováno v:
VDAT
A layout decomposition in Double Patterning Lithography (DPL) is considered to be potential for processing nodes at or below 32 nm. In this method, two features are assigned different colors corresponding to different exposures if the spacing between
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60d127db5b85a85aeaf66364858c810e
https://doi.org/10.1109/isvdat.2016.8064875
https://doi.org/10.1109/isvdat.2016.8064875
Autor:
Chong-Meng Huang, Shao-Yun Fang
Publikováno v:
2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
Self-aligned double patterning (SADP) is a leading lithography technology for sub-20 nm process nodes. For two-dimensional features, decomposability is hard to be guaranteed for an arbitrary layout. Therefore, SADP-aware layout legalization must be f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44f187d3349db66b20017732374e8f3d
https://doi.org/10.1109/vlsi-dat.2016.7482574
https://doi.org/10.1109/vlsi-dat.2016.7482574
Publikováno v:
ECS Transactions. 44:209-214
Due to the limitation of current lithography technology, double patterning lithography (DPL) has become the leading candidate for lithography process in sub-30nm integrated circuit (IC) manufacturing. Among all DPL technologies, self-aligned double p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0419de89ce3e2878808174919b31d09c
https://doi.org/10.1149/1.3694318
https://doi.org/10.1149/1.3694318