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Autor:
Oliver D. Patterson, Camille Xu, Abdalmohsen Elmalk, Kuo-Feng Pao, Kunyuan Chen, Double Chung, Fuming Wang, Shane Su, Andy Lan, Sudharshanan Raghunathan, Marc Kea, Jason Liao, Daniels Bae, Aiqin Jiang, Richer Yang, Wallace He
Publikováno v:
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV.
For advanced DRAM nodes, process window requirements have become extremely tight for Critical Dimension (CD) and Overlay. Determining process window based only on mean CD without quantifying defectivity on the wafer is no longer adequate. A superior