Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Donggwi Choi"'
Publikováno v:
Journal of the Institute of Electronics and Information Engineers. 50:137-147
In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebe47ee72ec72d98026b30a9b79d9bfd
https://doi.org/10.5573/ieek.2013.50.1.137
https://doi.org/10.5573/ieek.2013.50.1.137
Publikováno v:
2011 IEEE 9th International New Circuits and systems conference.
In this paper, a 10-b 500MS/s A/D converter (ADC) with a hybrid calibration and a new error correction logic is discussed. The proposed ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19beceb76297c635969a4d0b1edb4f81
https://doi.org/10.1109/newcas.2011.5981318
https://doi.org/10.1109/newcas.2011.5981318
Publikováno v:
2010 International SoC Design Conference.
In this paper, a 65nm 1.2V 7-bit 1GSPS A/D converter with a self-calibration technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2, interpolation rate is 8. An offset self-calibration circuit w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::386d7cf8a4e28f7d44a5374c144461d0
https://doi.org/10.1109/socdc.2010.5682940
https://doi.org/10.1109/socdc.2010.5682940
Publikováno v:
2010 International SoC Design Conference (ISOCC); 2010, p194-197, 4p