Zobrazeno 1 - 10
of 45
pro vyhledávání: '"Dong-Young Chang"'
Autor:
Dong-Young Chang, Ayman Shabra
Publikováno v:
CICC
This session presents multiple SAR-based ADC designs and one pipeline ADC. Various novel circuit techniques for residue amplification are demonstrated using auto-zeroing, positive feedback regeneration, voltage-to-time conversion, and ring amplifiers
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5c1f79fa44a2aefae7c947ce176a784
https://doi.org/10.1109/cicc.2017.7993702
https://doi.org/10.1109/cicc.2017.7993702
Autor:
Soon-Kyun Shin, Matthew Z. Straayer, Carlos E. Munoz, Jacques C. Rudell, Hae-Seung Lee, Denis C. Daly, Dong-Young Chang, Kush Gulati
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:1366-1382
A 12 bit 200 MS/s analog-to-digital converter (ADC) applies techniques of zero-crossing-based circuits as a replacement for high-gain high-speed op-amps. High accuracy in the residue amplifier is achieved by using a coarse phase in ZCBC followed by a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a28391701be1b81dc23d0644419a3a9
https://doi.org/10.1109/jssc.2014.2322853
https://doi.org/10.1109/jssc.2014.2322853
Autor:
Alfio Zanchi, Dong-Young Chang
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 55:2166-2177
A 16-bit 65-MS/s switched-capacitors pipeline analog-to-digital converter built in 0.45-mum 25-GHz fT complementary silicon-on-insulator BiCMOS delivers 80.1-dBFS signal-to-noise ratio, 98-dBc spurious-free dynamic range (SFDR) with 3-Vpp input range
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ad1f04109243312bfd9fc5f01522f42
https://doi.org/10.1109/tcsi.2008.920123
https://doi.org/10.1109/tcsi.2008.920123
Autor:
Matthew E. Brown, K. Takasuka, Un-Ku Moon, Gil-Cho Ahn, Naoto Ozaki, Hiroshi Youra, Gabor C. Temes, Koichi Hamashita, Dong-Young Chang, Ken Yamamura
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:2398-2407
A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11155e0038d891673de0cfb043933787
https://doi.org/10.1109/jssc.2005.856286
https://doi.org/10.1109/jssc.2005.856286
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 52:246-250
A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4ba317c48d9a5154281e90f41ba0444
https://doi.org/10.1109/tcsii.2005.843595
https://doi.org/10.1109/tcsii.2005.843595
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:960-969
An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6988344d00bd853dc28a03b3f327920
https://doi.org/10.1109/jssc.2004.842866
https://doi.org/10.1109/jssc.2004.842866
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 52:1-12
The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from ex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c937b5e51a6a5ec65108f26ed348d2a
https://doi.org/10.1109/tcsi.2004.839532
https://doi.org/10.1109/tcsi.2004.839532
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 51:2133-2140
This work describes a digital-domain self-calibration technique for multistage pipelined analog-to-digital converters (ADCs). By making the signal paths of both the input and the reference voltage the same, all error factors within a stage are merged
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b51365c4235e41306d52c9861fd75a9d
https://doi.org/10.1109/tcsi.2004.836863
https://doi.org/10.1109/tcsi.2004.836863
Autor:
Dong-Young Chang
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 51:2123-2132
Design techniques for a low-power pipelined analog-to-digital converters (ADC) without using a front-end sample-and-hold amplifier are presented. Two sampling topologies are compared that minimize aperture error by matching the time constant between
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f601a9c5619ec478044fe111d982e2f
https://doi.org/10.1109/tcsi.2004.836842
https://doi.org/10.1109/tcsi.2004.836842
Autor:
Un-Ku Moon, Dong-Young Chang
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:1401-1404
A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a728988d54b8953e1f0df78750835491
https://doi.org/10.1109/jssc.2003.814427
https://doi.org/10.1109/jssc.2003.814427