Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Dong-Soo Woo"'
Autor:
Young Jin Choi, Jong-Ho Lee, Byung-Gook Park, Dong-Soo Woo, Jong Duk Lee, Byung Yong Choi, Woo Young Choi
Publikováno v:
IEEE Transactions on Nanotechnology. 1:233-237
The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f865f647af0a7771649c09514e36cbf1
https://doi.org/10.1109/tnano.2002.807373
https://doi.org/10.1109/tnano.2002.807373
Publikováno v:
Journal of Information Display. 3:1-5
A CMOS driving circuit for active matrix type polymer electroluminescent displays was designed to develop an on‐chip microdisplay on the single crystal silicon wafer substrate. The driving circuit is a conventional structure that is composed of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::000d210563e0bc510668c4efb5744c72
https://doi.org/10.1080/15980316.2002.9651889
https://doi.org/10.1080/15980316.2002.9651889
Publikováno v:
IEEE Transactions on Electron Devices. 47:2326-2333
A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bdc0d0c0f246d72c2afcc4cc4a6ba17
https://doi.org/10.1109/16.887015
https://doi.org/10.1109/16.887015
Publikováno v:
IEEE Microwave and Wireless Components Letters. 14:83-85
We have proposed an improved and stable algorithm for linearity (V/sub IP3/) extraction by setting an optimized measurement node interval. This algorithm, considering the accuracy of measurement appliances, provides less noisy V/sub IP3/ without loss
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23d034d3944580e17023ac368adf810e
https://doi.org/10.1109/lmwc.2003.818527
https://doi.org/10.1109/lmwc.2003.818527
Publikováno v:
Japanese Journal of Applied Physics. 41:2345-2347
50 nm metal oxide semiconductor field effect transistors (MOSFETs) with two poly-Si side-gates are designed. We discuss the device structure and its fabrication process. Then, we investigate the improvement in device performance focusing on short cha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0bbbe870009937a73219048ce2ec8bd5
https://doi.org/10.1143/jjap.41.2345
https://doi.org/10.1143/jjap.41.2345
Autor:
Jong Duk Lee, Chilhee Chung, Chang-Woo Oh, Han Park, Byung-Gook Park, Yong Kyu Lee, Byung Yong Choi, Donggun Park, Dong-Soo Woo, Woo Young Choi
Publikováno v:
Conference Digest [Late News Papers volume included]Device Research Conference, 2004. 62nd DRC..
In this work, we fabricated twin silicon-oxide-nitride-oxide-silicon (SONOS) memory (TSM) cell transistors, based on the 90 nm non-volatile memory technology and showed the implementation of programmable threshold voltage (V/sub th/) MOSFETs in the n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7a0c9469afa85637b003d1455771db1
https://doi.org/10.1109/drc.2004.1367870
https://doi.org/10.1109/drc.2004.1367870
Publikováno v:
Conference Digest [Late News Papers volume included]Device Research Conference, 2004. 62nd DRC..
I-MOS uses modulation of the avalanche breakdown voltage of a gated p-i-n structure to control the output current. Because the p-n junction barrier lowering is not the mechanism of current flow control in the device, it can reduce the subthreshold sw
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe3f8beca5b1cc126af79d5885a4673d
https://doi.org/10.1109/drc.2004.1367869
https://doi.org/10.1109/drc.2004.1367869
Publikováno v:
Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412).
We have proposed a new extraction algorithm of linearity by optimizing measurement node interval, which provides noise-free VIP3 without significant detail loss. As a result, VIP3 can be easily derived satisfying one-percent error criterion. Stable V
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba8fcd296d6564157675ee5071720345
https://doi.org/10.1109/imtc.2003.1208183
https://doi.org/10.1109/imtc.2003.1208183
Publikováno v:
ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575).
30 nm nMOSFETs were fabricated on bulk-Si by processes for nanotechnology: the sidewall patterning technique, the RTO process and As/sub 2//sup +/ low energy implantation. With the aid of the sidewall patterning technique, very fine line patterns cou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3b09f9b752f2bad2a565925cf794e22
https://doi.org/10.1109/smelec.2002.1217818
https://doi.org/10.1109/smelec.2002.1217818
Autor:
Dae Hwan Kim, Dong-Soo Woo, Jae Sung Sim, Kyung Rok Kim, Sang-Hoon Lee, Byung-Gook Park, Jong Duk Lee, Ki-Whan Song, Gwanghyeon Baek
Publikováno v:
2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..
A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c432bfea6cc63c14e079daed9ccf1f7
https://doi.org/10.1109/nano.2003.1231729
https://doi.org/10.1109/nano.2003.1231729