Zobrazeno 1 - 10
of 58
pro vyhledávání: '"Donald Yeung"'
Autor:
Bruce Jacob, Mehdi Asnaashari, Luyi Kang, Donald Yeung, Devesh Singh, Sylvain Dubois, Candace Walden, Shang Li, Meenatchi Jagasivamani
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 18:1-26
Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employin
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 16:1-27
Heterogeneous microprocessors integrate a CPU and GPU on the same chip, providing fast CPU-GPU communication and enabling cores to compute on data “in place.” This permits exploiting a finer granularity of parallelism on the integrated GPUs, and
Autor:
Candace Walden, Luyi Kang, Devesh Singh, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob, Meenatchi Jagasivamani, Donald Yeung, Shang Li
Publikováno v:
IEEE Micro. 39:64-72
Nonvolatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint subarrays that leave the bul
Autor:
Meenatchi Jagasivamani, Devesh Singh, Luyi Kang, Mehdi Asnaashari, Bruce Jacob, Candace Walden, Donald Yeung, Sylvain Dubois
Publikováno v:
COOL CHIPS
Non-volatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU’s die. ReRAM bitcells are fabricated within crosspoint sub-arrays that leave the
Autor:
MINSHU ZHAO1 yeung@umd.edu, DONALD YEUNG1
Publikováno v:
ACM Transactions on Computer Systems. Jul2017, Vol. 35 Issue 2, p4:1-4:49. 49p.
Autor:
Abdel-Hameed A. Badawy, Donald Yeung
Publikováno v:
IEEE Computer Architecture Letters. 16:119-122
This work addresses the problem of optimizing graph-based programs for multicore processors. We use three graph benchmarks and three input data sets to characterize the importance of properly partitioning graphs among cores at multiple levels of the
Autor:
I. Stephen Choi, Donald Yeung
Publikováno v:
The Journal of Supercomputing. 73:2402-2429
To reduce power consumption in CPUs, researchers have studied dynamic cache resizing. However, existing techniques only resize a single cache within a uniprocessor or the shared last-level cache (LLC) within a multi-core CPU. To maximize benefits, it
Publikováno v:
High Performance Embedded Computing Handbook ISBN: 9781315221908
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f1e39109e7f5bbb2a0fb0b28fc21242
https://doi.org/10.1201/9781315221908-32
https://doi.org/10.1201/9781315221908-32
Autor:
Shang Li, Mehdi Asnaashari, Candace Walden, Bruce Jacob, Luyi Kang, Sylvain Dubois, Meenatchi Jagasivamani, Devesh Singh, Donald Yeung
Publikováno v:
MEMSYS
This paper presents the notion of a monolithic computer, a future computer architecture in which a CPU and a high-capacity main memory system are integrated in a single die. Such computers will become possible in the near future due to emerging non-v
Publikováno v:
ACM Transactions on Computer Systems. 34:1-30
To enable performance improvements in a power-efficient manner, computer architects have been building CPUs that exploit greater amounts of thread-level parallelism. A key consideration in such CPUs is properly designing the on-chip cache hierarchy.