Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Donald S. Miles"'
Autor:
Jay Hauser, Jimmie J. Wortman, Veena Misra, Brian E. Hornung, Xiaoli Xu, R. T. Kuehn, Donald S. Miles
Publikováno v:
Journal of Electronic Materials. 25:527-535
In the present study, we have performed electrical characterization of oxides deposited via rapid thermal chemical vapor deposition using SiH4 and N2O. We have investigated the effect of temperature, pressure, and SiH4 to N2O ratio on the electrical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49fe4fc0d8951b1aa69a6a6d89f37f9b
https://doi.org/10.1007/bf02666631
https://doi.org/10.1007/bf02666631
Publikováno v:
Journal of Electronic Materials. 21:805-810
Polycrystalline SiGe etches that are selective to silicon dioxide as well as silicon are needed for flexibility in device fabrication. A solution of NH4OH, H2O2, and H2O has been found to selectivity etch polycrystalline silicon-germanium alloys over
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cf00df402d25263b9fd6afda5363840
https://doi.org/10.1007/bf02665519
https://doi.org/10.1007/bf02665519
Autor:
Tad Grider, Clinton L. Montgomery, D. Mercer, Freidoon Mehrad, Donald S. Miles, Shaofeng Yu, Richard L. Guldi, B.Y. Lin, Yuqing Xu, Yaw S. Obeng, Sue E. Crank, D. Corum, A. J. Griffin, P J. Chen, F.S. Johnson, D.A. Ramappa, X. Liu, Jiong-Ping Lu, Thomas D. Bonifield, Juanita Deloach, Duofeng Yue, Lance S. Robertson, Lindsey H. Hall
Publikováno v:
2006 International Workshop on Junction Technology.
As CMOS technologies move into the 90nm node and beyond, nickel (Ni) self-aligned silicide (SALICIDE) is transitioning from R&D into mainstream SC fabrication. In this paper, advantages and challenges of Ni SALICIDE process technology will be reviewe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::59465f5a5541a0701c33e53de7ce1352
https://doi.org/10.1109/iwjt.2006.220877
https://doi.org/10.1109/iwjt.2006.220877
Autor:
Rajesh Khamankar, Joe G. Tran, P.E. Nicollian, Anand T. Krishnan, Melissa M. Hewson, S. Aur, Mark Somervell, James Walter Blatchford, Tad Grider, Lindsey H. Hall, Brian K. Kirkpatrick, D. Farber, Srinivasan Chakravarthi, Benjamen Michael Rathsack, H. Bu, Brian Hornung, Juanita Deloach, Brian A. Smith, Jiong-Ping Lu, C. Kaneshige, April Gurba, C. Bowen, C. Machala, Donald S. Miles, Husam N. Alshareef, M. J. Bevan, P.R. Chidambaram, Vladimir A. Ukraintsev, Ajith Varghese, Hiroaki Niimi
Publikováno v:
Scopus-Elsevier
In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7bea0f7129ea088a7c5308d5ef089297
https://doi.org/10.1109/vlsit.2004.1345456
https://doi.org/10.1109/vlsit.2004.1345456
Autor:
D. Mercer, Melissa M. Hewson, Tad Grider, Clinton L. Montgomery, R. Kuan, L. Tsung, Donald S. Miles, J. Ruan, J. Zhao, April Gurba, C.T. Lin, Jiong-Ping Lu, Y. Xu
Publikováno v:
Digest. International Electron Devices Meeting.
A novel nickel self-aligned silicide (SALICIDE) process technology has been developed for CMOS devices with physical gate length of sub-40 nm. The excess silicidation problem due to edge effect is effectively solved by using a low-temperature, in-sit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6eae55f6a0c71ccde57a5b0c8a7d2356
https://doi.org/10.1109/iedm.2002.1175855
https://doi.org/10.1109/iedm.2002.1175855
Autor:
Husam N. Alshareef, Juanita Deloach, M. J. Bevan, C. Bowen, M. Goodwin, P.R. Chidambaram, James Walter Blatchford, Srinivasan Chakravarthi, Tad Grider, Brian K. Kirkpatrick, Rajesh Khamankar, April Gurba, Ajith Varghese, Hiroaki Niimi, Donald S. Miles, Brian A. Smith, Xin Zhang, C. Machala, Jiong-Ping Lu, Lance S. Robertson, G.V. Thakar, Benjamen Michael Rathsack, Brian Hornung, P.E. Nicollian
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
A 90 nm logic technology is presented featuring an aggressively scaled 37 nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f9fff4d3ed93400052c81221e1ec69b
https://doi.org/10.1109/vlsit.2003.1221098
https://doi.org/10.1109/vlsit.2003.1221098
Publikováno v:
MRS Proceedings. 387
Rapid thermal chemical vapor deposition (RTCVD) has been investigated as an alternative to low pressure chemical vapor deposition (LPCVD) for formation of sidewall spacer dielectric. Silane (SiH 4 ) and tetraethylorthosilicate (TEOS) were chosen as t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02fbbc8086de44d9866ec0ea4ea91b28
https://doi.org/10.1557/proc-387-277
https://doi.org/10.1557/proc-387-277
Autor:
Donald S. Miles, Dennis M. Maher, D. Venables, G. Harris, Jim J. Wortman, M. R. Mirabedini, Jay Hauser
Publikováno v:
MRS Proceedings. 338
Rapid thermal chemical vapor deposition (RTCVD) oxides formed using TEOS and oxygen (O2) are compared with RTCVD oxides formed using silane (SiH4) and nitrous oxide (N2O). These oxides were deposited under varying pressure and gas composition to inve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec178fe4e48109e57c9ad421ee834526
https://doi.org/10.1557/proc-338-43
https://doi.org/10.1557/proc-338-43