Zobrazeno 1 - 10
of 70
pro vyhledávání: '"Donald F Canaperi"'
Autor:
Balasubramanian S. Pranatharthi Haran, B. Peethala, Kedari Matam, Kisik Choi, Nicholas A. Lanzillo, J. Casey, L. Chang, Terry A. Spooner, D. Janes, David L. Rath, Benjamin D. Briggs, Donald F. Canaperi, M. Packiam, Devika Sil, Hosadurga Shobha, Ryan Kevin J
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractor
Publikováno v:
2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
An exponential correlation is found to exist between the number of added defects on polished blanket wafers and the inverse of defect size for particulate CMP defects. Smaller surface defects are much more abundant and more difficult to remove. Pad s
Autor:
Maxwell Lippitt, Virat Mehta, Donald F. Canaperi, Jessica Gruss-Gifford, Oscar van der Straten, Gabriel Rodriguez
Publikováno v:
2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
This paper presents a multi-step process to improve the stability of plasma ignition of a magnetic target in a multi-cathode physical vapor deposition (PVD) system. Most target materials in the system have no issues igniting a stable plasma. The mate
Autor:
Hosadurga Shobha, Donald F. Canaperi, Chao-Kun Hu, Son V. Nguyen, Junedong Lee, Eric G. Liniger, Yongjin Yao, Griselda Bonilla, Chen Jia, Takeshi Nogami, Huai Huang, Stephan A. Cohen, B. Peethala, Theodorus E. Standaert, Thomas J. Haigh
Publikováno v:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
Mechanically robust low k C-rich SiCN and pSiCN dielectrics with excellent built-in Cu oxidation and diffusion barrier have been developed and evaluated as potential alternative low k Interlevel dielectrics for Cu interconnects. The novel low k dense
Autor:
Donald F. Canaperi, B. Peethala, Motoyama Koichi, Raghuveer R. Patlolla, Theodorus E. Standaert, Nicole Saulnier
Publikováno v:
ECS Journal of Solid State Science and Technology. 7:P397-P401
For better gap fill in beyond 56nm pitch Cu interconnect structures, Ru liner is one of the most promising solutions with better coverage and wettability. In this paper several new challenges in Ru CMP specific to ≤ 48nm pitch structures (also call
Autor:
John H. Zhang, Xie Ruilong, C. Labelle, Charan V. V. S. Surisetty, Pietro Montanini, Soon-Cheon Seo, Stan D. Tsai, Andrew M. Greene, Haigou Huang, Qiang Fang, Donald F. Canaperi, Wei-Tsu Tseng, Dinesh Koli, Walter Kleemeier, Dechao Guo, Jean E. Wynne, Matthew Malley, Raghuveer R. Patlolla
Publikováno v:
MRS Advances. 2:2361-2372
The CMP challenges for advanced technology nodes are discussed. Global and local uniformity challenges and their cumulative effects are presented. Uniformity improvements for advanced node integration were achieved through slurry, pad and platen opti
Autor:
Charan V. V. S. Surisetty, Stan D. Tsai, Steven Bentley, C. Labelle, John H. Zhang, Raghuveer R. Patlolla, Walter Kleemeier, Jody A. Fronheiser, Shariq Siddiqui, Donald F. Canaperi
Publikováno v:
MRS Advances. 2:2891-2902
As the scaling of the device dimensions in CMOS devices runs into physical limitations, new materials beyond Si with high electron and hole mobilities such as Ge, SiGe, and III-V materials are introduced. Challenges of CMP for these materials are rev
Autor:
Vimal Kamineni, Praneet Adusumilli, Adra Carr, Chengyu Niu, Shariq Siddiqui, Mark Raymond, Donald F. Canaperi, A. Arceo De La Pena, B. Peethala
Publikováno v:
Microelectronic Engineering. 173:22-26
In our study, we evaluate effective silicon and germanium oxide reduction by two surface treatments to achieve low contact resistivity at the semiconductor/metal interface. These chemistries, one alkaline and the other an acidic fluorine-based treatm
Publikováno v:
ECS Transactions. 75:5-13
Autor:
Shashank Sharma, Balasubramanian S. Pranatharthi Haran, Dechao Guo, Hemanth Jagannathan, Michael Chudzik, Kevin R. Winstel, Donald F. Canaperi, H.-J. Gossmann, Lan Yu, Samuel S. Choi, Shogo Mochizuki, Benjamin Colombeau, S.H. Lin, Abhishek Dube, Schubert S. Chu, J. Boland, F. Chang, Nicolas Loubet, M. Cogorno, D. McHerron, M. Stolfi, Richard A. Conti, Qu Jin, Sanjay Natarajan, Liu Patricia M, Zhenxing Bi, Z. Li
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to