Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Donald A. Priore"'
Autor:
Robert S. Orefice, Kevin Gillespie, Harry R. Fair, Stephen V. Kosonocky, Donald A. Priore, Samuel D. Naffziger, Sanjay Pant, Kathryn Wilcox, Ravinder Rachala, Jonathan White, Robert Cole, Benjamin Munger, Carson Henrion, Aaron Grenat, Ravi Jotwani
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:24-34
This work describes the physical design implementation of the AMD “Steamroller” module and adaptive clocking system that are both integral pieces of the AMD Kaveri APU SoC which was implemented using a 28 nm high-K metal gate Bulk CMOS process. T
Autor:
Kathryn Wilcox, Robert S. Orefice, Donald A. Priore, Stephen V. Kosonocky, Ravi Jotwani, Carson Henrion, Kevin Gillespie, Harry R. Fair, Jonathan White
Publikováno v:
ISSCC
The AMD two-core x86-64 CPU module, codenamed “Steamroller”, contains 236 million transistors implemented in 28nm high-κ metal gate (HKMG) bulk CMOS using 12 levels of metal. It is designed to operate from 0.8 to 1.45V. The CPU module occupies 2
Autor:
V. Rajagopalan, D.E. Dever, R. Witek, D.R. Meyer, S. Santhanam, S.M. Britton, R. Allmon, Donald A. Priore, D. Bertucci, L. Chao, B. Gieseke, M. Ladd, Edward J. McLellan, K. Kuchler, G. Hoeppner, L. Madden, Soha Hassoun, R.A. Conrad, R. Anglin, Daniel W. Dobberpuhl, S. Samudrala, J. Montanaro, B.M. Leary
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1555-1567
A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations. Fully pipelined an
Autor:
M.K. Gowan, J.B. Keller, B.J. Benschneider, Harry R. Fair, M.J. Smith, V. Peng, Kathryn Wilcox, Sharon M. Britton, R. Allmon, C.L. Houghton, Donald A. Priore, B. Gieseke, D.L. Leibholz, Jim Farrell, M.D. Matson, J.D. Clouser, T.H. Lee, R.J. Matthew, S.C. Lowell, M.D. Quinn, D.W. Bailey
Publikováno v:
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
A six-issue, four-fetch, out-of-order execution, 6OOMHz Alpha microprocessor achieves an estimated 40SpecInt95, 60SpecFP95 and 1800MB/s on McCalpin Stream. The 16.7x18.8mm2 die contains 15.2M transistors and dissipates an estimated 72W. It is in 2.0V
Autor:
L. O'Donnell, V. Sundaresan, Brian J. Campbell, Tuan Do, G. Yee, R. Blake, Donald A. Priore, N. Bunger, Daniel C. Murray, E. Supnet, D. Kidd, Ingino Joseph M, D. Rodriguez, M. Pearce, G. Yiu, Sribalan Santhanam, Jong Lee, M. Carlson, K. Anne, V. von Kaenel, J. Cheng, C. Vo, Robert Rogenmoser, S. Nishimoto, R. Wen, Dongwook Suh, Zongjian Chen, David A. Kruckemyer, M. Panich, Daniel W. Dobberpuhl, M. Oykher, R. Allmon
Publikováno v:
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major
Conference
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