Zobrazeno 1 - 10
of 63
pro vyhledávání: '"Dominic J. Schepis"'
This chapter discusses limits of gate dielectric scaling for advanced metal oxide semiconductor field effect transistor (MOSFET). We will review details of hafnium oxide (HfO2) gate oxide and how HfO2 can be modified to hafnium oxynitrides (HfON) and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17877364d4be9fac062d4da4145579e6
https://doi.org/10.1016/b978-0-12-812311-9.00005-0
https://doi.org/10.1016/b978-0-12-812311-9.00005-0
Publikováno v:
Applied Physics Letters. 113:032105
A highly precise band gap measurement based on deep UV spectroscopic ellipsometry along with Bruggeman effective model approximation was developed for high-k/metal gate CMOS with ultrathin EOT (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c50d9c0af68afdc1d1cc2df61f4e636c
https://doi.org/10.1063/1.5025829
https://doi.org/10.1063/1.5025829
Autor:
Eric C. T. Harley, Z. Zhu, Judson R. Holt, Matthew W. Stoker, R. Takalkar, L. Black, Rainer Loesing, A. Chakravarti, F. Yang, Dominic J. Schepis, James Chingwei Li, Xiaolin Chen, R. Murphy, Anita Madan, Thomas N. Adam, Abhishek Dube
Publikováno v:
ECS Transactions. 28:63-71
Uniaxial tensile strain in the channel enhances electron mobility and hence the drive current in an N-type field-effect transistor (NFET). For enhancement of NFET drive current via channel strain, the incorporation of embedded silicon carbon (eSi:C)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3cbe71f67a20208ceb5421c37d5d386
https://doi.org/10.1149/1.3375589
https://doi.org/10.1149/1.3375589
Autor:
Nivo Rovedo, Judson R. Holt, Sunfei Fang, Mark Lagus, Lynne Gignac, Angela Lamberti, Dominic J. Schepis, Anthony G. Domenicucci, Zhijiong Luo, Jinghong Li, Anita Madan, Henry K. Utomo, Jin-Ping Han, Chung Woh Lai, Ja-Hum Ku, Hung Ng
Publikováno v:
ECS Transactions. 16:545-549
Nano-beam diffraction (NBD) has been successfully used in measuring channel strain in device of embedded SiGe (eSiGe). Strain measurements have been correlated to different processing conditions and microstructures of eSiGe and device performance. Fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::69b083cf8a510e98ae15e0b2270acb62
https://doi.org/10.1149/1.2986811
https://doi.org/10.1149/1.2986811
Autor:
R. Takalkar, Anita Madan, Dominic J. Schepis, Eric C. Harley, Bin Yang, Abhishek Dube, Teresa L. Pinto, Zhibin Ren, Thomas N. Adam, Linda Black, Z. Zhu, Johan W. Weijtmans, Rainer Loesing, Jinghong Li, Ashima B. Chakravarti
Publikováno v:
ECS Transactions. 16:325-332
In addition to device scaling, strain engineering using SiC stressors in the S/D regions is important for nFET performance enhancement [1-3]. In this paper, we review the characterization of fully-strained epitaxial SiC and in-situ doped SiC:P films
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d314f9756c2842729e426ac06916377
https://doi.org/10.1149/1.2986790
https://doi.org/10.1149/1.2986790
Autor:
Scott Luning, Ashima B. Chakravarti, Z. Zhu, A. Gehring, Anita Madan, Alexander Reznicek, Guangrui Xia, R. Takalkar, Dan Mocuta, Dominic J. Schepis, B. Yang, Thomas N. Adam, E. Leobandung, Ka Kong Chan, J. Faltermeier, J. P. de Souza, Zhibin Ren, John Li, Rohit Pal, Eric C. Harley, Edward P. Maciejewski, Brian J. Greene, Abhishek Dube, D.-G. Park, M. Cai, D. K. Sadana, Linda Black, Bin Yang, Johan W. Weijtmans, G. Pei
Publikováno v:
ECS Transactions. 16:317-323
Summary In summary, this work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible. Key challenges lie in both high-quality ISPD eSi:C EPI development and modification of the conventional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::479e8a9b274b3fc5f4f083f4de0812c6
https://doi.org/10.1149/1.2986789
https://doi.org/10.1149/1.2986789
Autor:
E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, Dureseti Chidambarrao
Publikováno v:
2014 IEEE International Electron Devices Meeting.
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6233530b0b3fd6ddc14276a018716523
https://doi.org/10.1109/iedm.2014.7046977
https://doi.org/10.1109/iedm.2014.7046977
Autor:
Eduard A. Cartier, X. Chen, Pierre Malinge, L. Kang, T. Watanabe, Michael P. Belyansky, L. Economikos, O. Menut, Vijay Narayanan, C. Reddy, R. Divakaruni, Y.H. Park, Ravi Prakash Srivastava, M. Pallachalil, R. Koshy, Dominic J. Schepis, P. Montanini, Keith Kwong Hon Wong, M. Eller, Park Sejun, A. Ogino, H. Mallela, U. Kwon, T. Shimizu, W. Cote, Jay W. Strane, Srikanth Samavedam, M. Chae, Anurag Mittal, R. Sampson, J. Meiring, R. Joy, Huiling Shang, S. Soss, X. Yang, Keith H. Tabakman, M. Oh, W. Lai, C. Tran, S. Jain, E. Josse, D. Codi, H.V. Meer, B.Y. Kim, Jung-Geun Kim, Jin Bum Kim, C. Goldberg, Henry K. Utomo, J. Ciavatti, Barry Linder, R. Vega, W. Neumueller, J. Muncy, Kyung-hwan Cho, Scott J. Bukofsky, Alvin G. Thomas, Dinesh Koli, Katherina Babich, Bomi Kim, S. Lian, E. Alptekin, Y. Liu, S. H. Rhee, X. Wu, R. Arndt, W.L. Tan, Frederic Lalanne, Nam-Sung Kim, Ravikumar Ramachandran, K.Y. Lee, M.H. Nam, Randy W. Mann, Il-Ryong Kim, Yujun Li, V. Sardesai, Siddarth A. Krishnan, C. Tian, D. Levedakis, Seung-Kwon Kim, Jedon Kim, M. Celik, F. Matsuoka, M. Weybright, J. Sudijono, M. Aminpur, B. Hamieh, Greg Northrop, J.W. Lee
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ec874734f9fcf487e547466890b1297
https://doi.org/10.1109/vlsit.2012.6242495
https://doi.org/10.1109/vlsit.2012.6242495