Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and Beyond.

Autor: Jin Cai, Majumdar, A., Dobuzinsky, D., Ning, T.H., Koester, S.J., Haensch, W.E.

Publikováno v: 2007 IEEE International Electron Devices Meeting; 2007, p907-910, 4p

Structural demonstration of cost effective isolation trench fill for sub-110 nm vertical trench DRAM and SOC applications.

Autor: Yang, S.-W., Liao, W.-S., Economikos, L., Guliani, A., Yang, D., Kim, B.-Y., Dobuzinsky, D., Shih, S.

Publikováno v: 2003 International Symposium on VLSI Technology, Systems & Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672); 2003, p117-120, 4p

Ultrathin RTP Oxynitride Dielectrics on Planar, Trench and Three Dimensional Structures.

Autor: Nguyen, Son V., Nguyen, Tue, Carl, D., Pricer, D., Korejwa, J. W., Dobuzinsky, D.

Publikováno v: ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference; 1995, p251-254, 4p

Cleans for Al vias in a 0.175 /spl mu/m dual damascene process.

Autor: Gambino, J., Clevenger, L., Costrini, G., Schnabel, F., Ravikumar, R., Dobuzinsky, D., Iggulden, R., Dziobkowski, C., Wildman, H., Benedict, J., Bruley, J., Domenicucci, A.

Publikováno v: Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat No99EX247); 1999, p206-208, 3p

CVD of fluorosilicate glass for ULSI applications

Autor: Shapiro, M. J., Nguyen, S. V., Matsuda, T., Dobuzinsky, D.

Publikováno v: Thin Solid Films; 1995, Vol. 270 Issue: 1 p503-507, 5p