Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Dmitry Burlyaev"'
Autor:
Serafima Y. Ryzhenkova, Oleksandr I. Ivankov, Dmitry Burlyaev, Meir Yerdauletov, K. V. Mironovich, Svetlana Bocharova, Filipp S. Napolskiy, Mikhail V. Avdeev, V. A. Krivchenko, Balken Talgatbekovna Kaparova
Publikováno v:
Energy Technology. 8:2000146
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d4507f2158c292ac2faa66329ad8f17
https://doi.org/10.1002/ente.202000146
https://doi.org/10.1002/ente.202000146
Autor:
Dmitry Burlyaev, Rene van Leuken
Publikováno v:
Microelectronics Journal. 45:1335-1341
Fault-tolerance analysis reveals possible system behavior under the influence of faults. Such analysis is essential for satellites where faults might be caused by space radiation and autonomous recovery is needed. In this paper we present a statistic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b78039fcc60328a1ea9d76d4095f50a
https://doi.org/10.1016/j.mejo.2014.01.007
https://doi.org/10.1016/j.mejo.2014.01.007
Autor:
Dmitry Burlyaev, Pascal Fradet
Publikováno v:
Formal Methods in Computer-Aided Design (FMCAD 2015)
Formal Methods in Computer-Aided Design (FMCAD 2015), Sep 2015, Austin, Texas, United States
FMCAD
Formal Methods in Computer-Aided Design (FMCAD 2015), Sep 2015, Austin, Texas, United States
FMCAD
International audience; We present a language-based approach to certify fault-tolerance techniques for digital circuits. Circuits are expressed in a gate-level Hardware Description Language (HDL), fault-tolerance techniques are described as automatic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ca6156458ea1caa2433a0ece2e46c36e
https://hal.inria.fr/hal-01253127
https://hal.inria.fr/hal-01253127
Publikováno v:
2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. ⟨10.1109/AHS.2015.7231164⟩
AHS
2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. ⟨10.1109/AHS.2015.7231164⟩
AHS
International audience; We present a novel logic-level circuit transformation technique for the automatic insertion of fault-tolerance properties. The transformations, based on time-redundancy, allow dynamic changes of the level of redundancy without
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a2f0572fce74b7201032709fd2c2378e
https://hal.inria.fr/hal-01253111
https://hal.inria.fr/hal-01253111
Publikováno v:
Design, Automation and Test in Europe Conference, DATE'14
Design, Automation and Test in Europe Conference, DATE'14, Mar 2014, Dresden, Germany
Design, Automation and Test in Europe Conference, DATE'14, Mar 2014, Dresden, Germany
in DATE 2014 : Design Automation and Test in Europe (to appear); International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::863ef15146bc420987f7a194b56fadeb
https://doi.org/10.7873/date2014.105
https://doi.org/10.7873/date2014.105