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pro vyhledávání: '"Dmitry Alexeevitch Lebedev"'
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 67-76 (2019)
State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency. An implementation of memory subsystem in HDL (hardware description language) is complex and erro
Externí odkaz:
https://doaj.org/article/b41b9ad177b24aebb9b6de5ceb976d61
