Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Dmitri Mironov"'
Autor:
Victor Stepanenko, Klaus D. Jöhnk, Ekaterina Machulskaya, Marjorie Perroud, Zack Subin, Annika Nordbo, Ivan Mammarella, Dmitri Mironov
Publikováno v:
Tellus: Series A, Dynamic Meteorology and Oceanography, Vol 66, Iss 0, Pp 1-18 (2014)
Five one-dimensional (1D) lake models were run for the open water season in 2006 for Lake Valkea-Kotinen (Finland) using on-lake measured meteorological forcing. The model results were validated using measurements of water temperature and of eddy cov
Externí odkaz:
https://doaj.org/article/478d64f637934a9094756453335a3e6e
Publikováno v:
IDT
A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented for modeling sequential circuits for fault simulation purposes. The size of S BDD is in linear correlation with the circuit size and is characterized by the propert
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d144c1590051eadedea8867a2819d39
https://doi.org/10.1109/idt.2014.7038600
https://doi.org/10.1109/idt.2014.7038600
Publikováno v:
ETS
A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7dd74f1a902b4d37fc26f1fb21d0ba3c
https://doi.org/10.1109/ets.2014.6847825
https://doi.org/10.1109/ets.2014.6847825
Autor:
Raimund Ubar, Dmitri Mironov
Publikováno v:
DDECS
A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented as an extension of the SSBDDs, and a method is given to minimize the size of the model. As in case of SSBDDs, the S3BDDs have linear complexity compared to the size
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44c93696ff588ae3e15afb1b3717c162
https://doi.org/10.1109/ddecs.2014.6868767
https://doi.org/10.1109/ddecs.2014.6868767
Publikováno v:
2011 IEEE International Conference on Computer Science and Automation Engineering.
The complexity of today's VLSI chip designs makes verification a necessary step before fabrication. As a result, gate-level logic simulation has become an integral component of the VLSI circuit design process which verifies the design and analyzes it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64229a84bf4cf76b4ed2dc40c270908e
https://doi.org/10.1109/csae.2011.5952643
https://doi.org/10.1109/csae.2011.5952643
Publikováno v:
DSD
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. In this paper a new algorithm for parallel logic simulation is proposed based on a new model of Structurally Synthesized Multiple Input BDDs (SSM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::165fda719737e91536ddd03eb3af6613
https://doi.org/10.1109/dsd.2010.27
https://doi.org/10.1109/dsd.2010.27
Publikováno v:
ISCAS
The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c8023e6220fb634928e88f28dfef49f
https://doi.org/10.1109/iscas.2010.5537504
https://doi.org/10.1109/iscas.2010.5537504
Publikováno v:
ISQED
The paper presents a new structural fault-independent fault collapsing method based on the topology analysis of the circuit, which has linear complexity. The minimal necessary set of faults as the target objective for test generation is found. The ma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5a8f95766fb952d9ccd97ff5a308eee
https://doi.org/10.1109/isqed.2010.5450451
https://doi.org/10.1109/isqed.2010.5450451
Publikováno v:
ICECS
Binary Decision Diagrams (BDD) have become the state-of-the-art data structure in VLSI CAD for representation and manipulation of Boolean Functions. For verification, fault simulation and test generation purposes structurally synthesized BDDs (SSBDD)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e8a12814e09b8118489d6470049db6c
https://doi.org/10.1109/icecs.2009.5410895
https://doi.org/10.1109/icecs.2009.5410895
Autor:
Annika Nordbo, Ivan Mammarella, Victor Stepanenko, Zack M Subin, Dmitri Mironov, Marjorie Perroud, Klaus Jöhnk, Ekaterina Machulskaya
Publikováno v:
Tellus A; Vol 66 (2014)
Tellus: Series A, Dynamic Meteorology and Oceanography, Vol 66, Iss 0, Pp 1-18 (2014)
Tellus: Series A, Dynamic Meteorology and Oceanography, Vol 66, Iss 0, Pp 1-18 (2014)
Five one-dimensional (1D) lake models were run for the open water season in 2006 for Lake Valkea-Kotinen (Finland) using on-lake measured meteorological forcing. The model results were validated using measurements of water temperature and of eddy cov
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::395f395449fb3c21d82f811f05d8fe1b
https://doi.org/10.3402/tellusa.v66.21389
https://doi.org/10.3402/tellusa.v66.21389