Contributions to the analysis and design of an ADPLL

Autor: Joubert, C., Bercher, Jean-François, Baudoin, G., Divel, T., Ramet, S., Level, P.

Publikováno v: 13th IEEE International Conference on Electronics, Circuits, and Systems (ICECS'06)
13th IEEE International Conference on Electronics, Circuits, and Systems (ICECS'06), 2006, France. pp.322-325

International audience

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::13daefbaf9dd12b5b1a34f09fab62354
https://hal.archives-ouvertes.fr/hal-00621912

3D integration demonstration of a wireless product with design partitioning.

Autor: Druais, G., Ancey, P., Aumont, C., Caubet, V., Chapelon, L.-L., Chaton, C., Cheramy, S., Cordova, S., Cirot, E., Colonna, J.-P., Coudrain, P, Divel, T., Dodo, Y., Farcy, A., Guitard, N., Haxaire, K., Hotellier, N., Leverd, F., Liou, R., Michailos, J.

Publikováno v: 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International; 1/ 1/2011, p1-5, 5p

Distributed MOS varactor biasing for VCO gain equalization in 0.13 μm CMOS technology.

Autor: Mira, J., Divel, T., Ramet, S., Begueret, J.-B., Deval, Y.

Publikováno v: 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers; 2004, p131-134, 4p

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