Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Dinesh Kushwaha"'
Autor:
Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:2311-2315
Autor:
Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, S. Dasgupta, Anand Bulusu
Publikováno v:
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID).
Autor:
Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu
Publikováno v:
2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS).
Autor:
Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv Joshi, Sudeb Dasgupta, Anand Bulusu
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS).
Autor:
D. K. Mishra, Dinesh Kushwaha
Publikováno v:
Circulation in Computer Science. 2:1-4
This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with
Autor:
D. K., Dinesh Kushwaha
Publikováno v:
Communications on Applied Electronics. 6:10-13
Autor:
Dinesh Kushwaha, D. K. Mishra
Publikováno v:
International Journal of Computer Applications. 148:26-29
Autor:
D. K. Mishra, Dinesh Kushwaha
Publikováno v:
2017 14th IEEE India Council International Conference (INDICON).
This work depends on the principle of temperature compensation of threshold voltage of MOS transistor. It generates constant voltage 509mV with supply voltage range 0.7V - 1.8V. It is implemented at 180nm in cadence EDA tool. The device has MOS trans
Autor:
D. K. Mishra, Dinesh Kushwaha
Publikováno v:
2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC).
A Nano power CMOS voltage generator circuit has been implemented using a 0.18μm standard CMOS process technology. The circuit has MOSFETs operated in sub threshold region without resistor. It works on the concept of temperature compensation of thres
Autor:
Dinesh Kushwaha, D. K. Mishra
Publikováno v:
ICIIS
This work depends on the principle of temperature compensation of threshold voltage of MOS transistor. It generates constant voltage 333mV with supply voltage range 0.8 V–1.3V. It is implemented at 180nm in cadence EDA tool. The device has MOS tran