Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Dimitris Kaseridis"'
Publikováno v:
IEEE Micro. 31:90-98
To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a fo
Publikováno v:
PACT
To achieve high efficiency and prevent destructive interference among multiple divergent workloads, the last-level cache of Chip Multiprocessors has to be carefully managed. Previously proposed cache management schemes suffer from inefficient cache c
Publikováno v:
SIGMETRICS
The workloads in modern Chip-multiprocessors (CMP) are becoming increasingly diversified, creating different resource demands on hardware substrate. It is necessary to allocate hardware resources based on the needs of the workloads in order to improv
Publikováno v:
MICRO
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors. DRAM is ubiquitous as a main memory technology, but while DRAM’s per-chip density and frequency continue to scale, the
Publikováno v:
PACT
To effectively design a computer system for the worst case power consumption scenario, system architects often use hand-crafted maximum power consuming benchmarks at the assembly language level. These stressmarks, also called power viruses, are very
Publikováno v:
ISCA
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU's data needs, and are mostly oblivious to the main memory. In this paper, we demonstrate t
Publikováno v:
HPCA
By integrating multiple cores in a single chip, Chip Multiprocessors (CMP) provide an attractive approach to improve both system throughput and efficiency. This integration allows the sharing of on-chip resources which may lead to destructive interfe
Publikováno v:
ICPP
As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip. This enables sharing of computation resources that was not previously possib
Publikováno v:
ISQED
A novel technique for reducing the test sequences of reseeding-based schemes is presented in this paper. The proposed technique is generic and can be applied to test set embedding or mixed-mode schemes based on various TPG. The imposed hardware overh