Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Diego Calvo Ruiz"'
Autor:
Daxin Han, Giorgio Bonomo, Diego Calvo Ruiz, Akshay Mahadev Arabhavi, Olivier J. S. Ostinelli, Colombo R. Bolognesi
Publikováno v:
IEEE Transactions on Electron Devices, 69 (7)
Digital electronics power consumption evolved into a major concern: at the current pace, general-purpose computing energy consumption will exceed global energy production before 2045. The principal approach to curbing energy consumption in digital ap
Autor:
Diego Calvo Ruiz, Carmine Sileno
Publikováno v:
Materials Science Forum. 1062:155-159
The present paper shows a new fixed abrasive bond-grit formulation aimed for best-in-class, low-cost and high-quality finished SiC wafer surfaces. Grinding wheels manufactured with this technology can accomplish ultra-smooth SiC (Ra = 0.55 nm and TTV
Autor:
Giorgio Bonomo, Daxin Han, Olivier Ostinelli, Diego Calvo Ruiz, Tamara Saranovac, Colombo R. Bolognesi
Publikováno v:
IEEE Electron Device Letters. 41:1320-1323
GaInAs-based Metal Oxide Semiconductor High Electron Mobility Transistors (MOS-HEMTs) can in principle combine the wide bandwidth of HEMTs to the low gate leakage current of MOSFETs in a single deeply-scaled ultrahigh speed low-noise technology. Desp
Autor:
Daxin Han, Giorgio Bonomo, Diego Calvo Ruiz, Akshay Mahadev Arabhavi, Olivier J. S. Ostinelli, Colombo R. Bolognesi
Publikováno v:
IEEE Transactions on Electron Devices, 69 (7)
Part I of this work described narrow bandgap GaInAs-based I-MOS devices with a minimum steep slope SSmin = 1.25 mV/dec maintained over 4 orders of magnitude in drain current, ION/IOFF ratios >106 at 300 K (>109 at 15 K), and low operating voltages fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d9aee6e7023f575a4fa1b9dca1d00694
Autor:
Olivier Ostinelli, Daxin Han, Akshay M. Arabhavi, Colombo R. Bolognesi, Anna Hambitzer, Tamara Saranovac, Diego Calvo Ruiz
Publikováno v:
IEEE Transactions on Electron Devices, 66 (11)
GaInAs/InAs composite channels in InP-based pHEMTs enable wideband and/or low-noise performances because of their superior carrier transport properties. To date, the influence of the InAs inset design details on transistor performance has not been pa
Autor:
Olivier Ostinelli, Tamara Saranovac, Daxin Han, Diego Calvo Ruiz, Colombo R. Bolognesi, Akshay M. Arabhavi
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 32:496-501
Optimum device performance in terms of noise and gain of AlInAs/GaInAs/InP High Electron Mobility Transistors (HEMTs) requires minimizing the contact resistance ${R} _{C}$ . In several HEMT fabrication steps in device manufacturing it is common to ex
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 30:462-467
A Pt/Ti/Pt/Au gate electrode stack is commonly used in AlInAs/GaInAs/InP high electron mobility transistors due to the high Schottky barrier height of Pt on AlInAs and the fact that Pt can be controllably diffused through semiconductor layers thereby
Publikováno v:
BCICTS
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)
InP-based HEMTs with composite GaInAs/InAs channels are recognized for their high frequency performance thanks to their superior carrier transport properties. On the other hand, the addition of an InP subchannel to a GaInAs channel can effectively su
Autor:
Giorgio Bonomo, Colombo R. Bolognesi, Daxin Han, Tamara Saranovac, Olivier Ostinelli, Diego Calvo Ruiz
Publikováno v:
physica status solidi (a). 218:2000191
Autor:
Luis A. Marqués, Normand Mousseau, María Aboy, Diego Calvo Ruiz, Iván Santos, Lourdes Pelaz, Mickaël Trochet, Pedro López
Producción Científica
The modeling of self-interstitial defects evolution is key for process and device optimization. For a self-interstitial cluster of a given size, several configurations or topologies exist, but conventional models assume t
The modeling of self-interstitial defects evolution is key for process and device optimization. For a self-interstitial cluster of a given size, several configurations or topologies exist, but conventional models assume t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bece52f77a4973f28889d90e292b2a03
https://doi.org/10.1109/cde.2017.7905224
https://doi.org/10.1109/cde.2017.7905224