Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Didier Lattard"'
Autor:
Benoit Sklenard, Bastien Giraud, Sebastien Thuries, Mikael Casse, Joris Lacord, Cm. Ribotta, V. Lapras, P. Acosta-Alba, O. Billoint, M. Mouhdach, N. Rambal, Pascal Besson, Francois Andrieu, Perrine Batude, Didier Lattard, Laurent Brunet, Gilles Sicard, Xavier Garros, Christoforos G. Theodorou, L. Brevard, Maud Vinet, V. Mazzocchi, P. Sideris, M. Ribotta, Claire Fenouillet-Beranger, F. Ponthenier, Pascal Vivet, Sebastien Kerdiles, G. Cibrario, J.M. Hartmann, Frank Fournel, Bernard Previtali, Frédéric Mazen, Claude Tabone
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC)
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a896dcadaa6b8a425398da1a162204f
https://hal.archives-ouvertes.fr/hal-03434018
https://hal.archives-ouvertes.fr/hal-03434018
Autor:
Guillaume Moritz, Gael Pillonnet, Frédéric Berger, Denis Dutoit, Alexandre Arriordaz, David Coriat, Lucile Arnaud, Julian Pontes, Eric Guthmuller, Christian Bernard, Fabien Clermidy, Alexis Farcy, Didier Varreau, P. Coudrain, Alain Greiner, J. Durupt, Michel Harrand, Didier Lattard, Quentin L. Meunier, Jean Charbonnier, Ivan Miro-Panades, Sebastien Thuries, Cesar Fuguet, Arnaud Garnier, Severine Cheramy, Alain Gueugnot, Pascal Vivet, Yvain Thonnart
Publikováno v:
IEEE Journal of Solid-State Circuits
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
IEEE Journal of Solid-State Circuits, 2021, 56 (1), pp.79-97. ⟨10.1109/JSSC.2020.3036341⟩
In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d4012e9cdfa24d7a486fffa94ba46e77
https://hal.archives-ouvertes.fr/hal-03072959/document
https://hal.archives-ouvertes.fr/hal-03072959/document
Autor:
Severine Cheramy, P.-Y. Martinez, A. Philippe, P. Coudrain, Yvain Thonnart, Arnaud Garnier, Fabien Clermidy, Eric Guthmuller, Pascal Vivet, Denis Dutoit, Didier Lattard, Jean Charbonnier
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM)
2020 IEEE International Electron Devices Meeting (IEDM), Dec 2020, San Francisco, United States. pp.15.3.1-15.3.4, ⟨10.1109/IEDM13553.2020.9372037⟩
2020 IEEE International Electron Devices Meeting (IEDM), Dec 2020, San Francisco, United States. pp.15.3.1-15.3.4, ⟨10.1109/IEDM13553.2020.9372037⟩
Supercomputers will soon achieve Exascale-level computing performances mainly thanks to the introduction of innovative hardware technologies around the processors. This article explains architectural and performance evolutions and describes how 3D in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6975e2d9dd986db359f87512f6a17c97
https://cea.hal.science/cea-03759943
https://cea.hal.science/cea-03759943
Autor:
F. Andrieu, M. Ezzadeen, S. Barraud, J.-P. Noel, D. Bosch, Bastien Giraud, J. Lacord, J.-M. Portal, Didier Lattard
Publikováno v:
IEEE Transactions on Electron Devices
The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed bas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5e2d310202f806274e52ffb560f28948
http://arxiv.org/abs/2012.00061
http://arxiv.org/abs/2012.00061
Autor:
Didier Lattard, Perrine Batude, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Sebastien Thuries, O. Billoint
Publikováno v:
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1740-1745, ⟨10.23919/DATE48585.2020.9116293⟩
DATE
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.1740-1745, ⟨10.23919/DATE48585.2020.9116293⟩
DATE
International audience; Monolithic 3D (M3D) stands now as the ultimate technology to side step Moore's Law stagnation. Due to its nanoscale Monolithic Inter-tier Via (MIV), M3D enables an ultrahigh density interconnect between Logic and Memory that i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bcd07b880c4d57be5bc03a52b15c7a8e
https://cea.hal.science/cea-03288836
https://cea.hal.science/cea-03288836
Autor:
F. Balestra, C. Perrot, Joris Lacord, Didier Lattard, Perrine Batude, Benoit Sklenard, V. Benevent, P. Acosta Alba, Sebastien Kerdiles, D. Bosch, Claire Fenouillet-Beranger, J. Lassarre, J. Richy, Francois Andrieu, J.-P. Colinge, Laurent Brunet
Publikováno v:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-sili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c9ce1f179d7606adeb1a27fcb299c07c
Autor:
J. Durupt, Dominique Drouin, Yann Beilliard, P.-Y. Martinez, Severine Cheramy, David Danovitch, A. Philippe, Arnaud Garnier, P. Coudrain, C. Fuguet Tortolero, Pascal Vivet, Denis Dutoit, Didier Lattard, Jean Charbonnier, Maxime Godard, V. Mengue, Eric Guthmuller
Publikováno v:
2020 IEEE Symposium on VLSI Technology
2020 IEEE Symposium on VLSI Technology, Jun 2020, Honolulu, IEEE, pp.1-2, 2020, ⟨10.1109/VLSITechnology18217.2020.9265100⟩
2020 IEEE Symposium on VLSI Technology, Jun 2020, Honolulu, IEEE, pp.1-2, 2020, ⟨10.1109/VLSITechnology18217.2020.9265100⟩
In the context of high performance computing (HPC), energy efficiency and computing density are key for targeting exascale architectures. Close integration of chiplets, active interposer and field programmable gate arrays (FPGA) paves the way for den
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a8eb74a04d96315b4fab0e767614ffcd
https://hal.archives-ouvertes.fr/hal-03178715
https://hal.archives-ouvertes.fr/hal-03178715
Publikováno v:
3DIC
3D integration is a promising solution to meet the increased need for functionality, density and performance of future integrated circuits. It is an attractive technique to address the requirements of several applications such as smart imagers, high-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2641e3f66f1da43e7425d56c59711eb
https://doi.org/10.1109/3dic48104.2019.9058864
https://doi.org/10.1109/3dic48104.2019.9058864
Publikováno v:
ETS
Test infrastructure of High-Density Three-Dimensional Integrated Circuits (HD 3D-IC) present a new test challenges because of the high interconnect density and the area cost for test features. In this work, we firstly present a pre-analysis of the te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2da99728e11b20a927628c3279827957
https://doi.org/10.1109/ets.2019.8791531
https://doi.org/10.1109/ets.2019.8791531
Autor:
Didier Campos, P. Coudrain, Yorrick Exbrayat, Lucile Arnaud, Stephane Minoret, F. Ponthenier, Andrea Vinci, Severine Cheramy, Alain Gueugnot, Daniel Scevola, Cesar Fuguet Tortolero, P. Chausse, Roselyne Segaud, Giovanni Romano, Christophe Aumont, Didier Lattard, Jean Charbonnier, Pierre-Emile Philip, C. Ribiere, Arnaud Garnier, Jean Michailos, Mathilde Gottardi, Raphael Eleouet, Frédéric Berger, Eric Guthmuller, Gilles Simon, Jerome Beltritti, Gilles Romero, Maxime Argoud, Denis Dutoit, Alexis Farcy, Nacima Allouti, Therry Mourier, Remi Velard, Pascal Vivet, Corinne Legalland
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interco
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8afe955b96b263c988971d8f1f91372
https://doi.org/10.1109/ectc.2019.00092
https://doi.org/10.1109/ectc.2019.00092