Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Di-Son Kuo"'
Autor:
Chung Wang, J.P Wu, Ching-Hsiang Hsu, Juang-Ke Yeh, H.J Tao, D.S Shyu, C.S Tsai, T.J Fong, Michael Liang, Wen-Ting Chu, S.H Lin, Y.D Chih, S.P Peng, Chia-Ta Hsieh, Hung-Cheng Sung, Sam Chu, Y.C Huang, Chen Hsin-Ming, Di-Son Kuo, Chrong Jun Lin, S.C Wong, Y.T Chen, K.Y Lee
Publikováno v:
Microelectronic Engineering. 59:203-211
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::77c300a992f2a3159d3aaeb6147d3034
https://doi.org/10.1016/s0167-9317(01)00623-2
https://doi.org/10.1016/s0167-9317(01)00623-2
Autor:
Chung S. Wang, Shyh-Fann Ting, Kuo-Ching Huang, Y. P. Hsu, Chung-Hui Chen, Mong-Song Liang, Yean-Kuen Fang, Yvonne Lin, Di-Son Kuo, Dun-Nian Yaung
Publikováno v:
Solid-State Electronics. 45:297-301
The program speed of a selected cell and the program disturbance of unselected cells sharing the common program-line in split-gate source-side injected flash memory has been investigated. It is found that the program disturbance becomes severe as the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::98128fb0fcf361b3ac62e493fae7d1fc
https://doi.org/10.1016/s0038-1101(01)00009-0
https://doi.org/10.1016/s0038-1101(01)00009-0
Autor:
Di-Son Kuo, Dun-Nian Yang, Chii-Wen Chen, Hung-Cheng Sung, Kuo-Ching Huang, Yean-Kuen Fang, C.S. Wang, Mong-Song Liang
Publikováno v:
IEEE Electron Device Letters. 21:359-361
In this paper, the "erase" degradation in program/erase (P/E) cycling endurance of split-gate flash memory has been investigated. It is found that increasing the control-gate (CG) voltage (V/sub CG/) during erasing can slow down the "window closure"
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1164b3b661c50216a652970ab92307f4
https://doi.org/10.1109/55.847380
https://doi.org/10.1109/55.847380
Autor:
Dun-Nian Yaung, Hung-Cheng Sung, Kuo-Ching Huang, C.S. Wang, Mong-Song Liang, Chii-Wen Chen, Di-Son Kuo, Yean-Kuen Fang
Publikováno v:
IEEE Electron Device Letters. 20:412-414
The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed signi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f97810073b9dde2fba62725b214d8fb0
https://doi.org/10.1109/55.778161
https://doi.org/10.1109/55.778161
Autor:
J.Y.-C. Sun, John Yeh, Boon-Khim Liew, J.R. Shih, K.R. Peng, Di-Son Kuo, M.C. Ho, J.H. Lee, H.D. Su, S.H. Chen
Publikováno v:
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).
The electrons and holes trapped in the tunneling oxide and interface states generated in the Si-SiO/sub 2/ interface during program/erase (P/E) operations are known to cause reliability problems which can deteriorate the cell performance and cause V/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af8697f797bcc30a88e020bf5155ed1b
https://doi.org/10.1109/relphy.1999.761587
https://doi.org/10.1109/relphy.1999.761587
Publikováno v:
Proceedings of 1994 VLSI Technology Symposium.
A novel three-dimensional flash EEPROM cell named the TEFET (Trench Embedded Field Enhanced Tunneling) has been developed for ultra high density memory applications. The cell technology is compatible with standard CMOS processes. It provides very sma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d11db4341b43cc33a3148a0b6879957
https://doi.org/10.1109/vlsit.1994.324382
https://doi.org/10.1109/vlsit.1994.324382
Publikováno v:
Electronics Letters. 35:1112
The effect of post poly-Si N/sub 2/O annealing on the programming performance and reliability of split-gate source-side-injection EEPROM/flash memory cells has been investigated. It is found that by employing post-poly-Si gate N/sub 2/O annealing, th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eae178101199e364fce9ce427a8eea10
https://doi.org/10.1049/el:19990711
https://doi.org/10.1049/el:19990711
Autor:
Chenming Hu, D. Giandomenico, K.A. Sassaman, R. Bregar, Jeong Yeol Choi, Di-Son Kuo, S.P. Sapp
Publikováno v:
IEEE Electron Device Letters. 6:211-214
Since the turn-off speed of the new bipolar-MOS power transistor is slow compared to that of a MOSFET, it is important to understand the limiting mechanism and the prospect for future improvement. In this letter, it is demonstrated that the turnoff w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ef14f260106877d9d38b5ef1222b13d
https://doi.org/10.1109/edl.1985.26101
https://doi.org/10.1109/edl.1985.26101
Publikováno v:
Solid-State Electronics. 29:1229-1237
This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current densi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5dbabcd2300c5f83757a20f8bd07bf6b
https://doi.org/10.1016/0038-1101(86)90128-0
https://doi.org/10.1016/0038-1101(86)90128-0
Autor:
Chenming Hu, Di-Son Kuo
Publikováno v:
IEEE Electron Device Letters. 7:510-512
This is a theoretical study of the effect of epitaxial layer design on the performance of the power bipolar-MOS transistor, also known as IGT and COMFET. A procedure for optimizing the layer thicknesses, doping concentrations, and lifetime is propose
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef9e08569769ef4a53fdd31973f547c5
https://doi.org/10.1109/edl.1986.26455
https://doi.org/10.1109/edl.1986.26455