Zobrazeno 1 - 10
of 89
pro vyhledávání: '"Dhrystone"'
Autor:
Satyajit Bora, Roy Paily
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:2132-2136
Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f5ffe743c4dad292c32e7e865a202df
https://doi.org/10.1109/tcsii.2020.3043204
https://doi.org/10.1109/tcsii.2020.3043204
Autor:
Uwe Meyer-Baese
Publikováno v:
Embedded Microprocessor System Design using FPGAs ISBN: 9783030505325
This chapter gives an overview of the Altera Nios microprocessor system design, its architecture, and instruction set. It starts with a brief Nios history followed by ISA architecture and interesting design features such as custom instructions.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64815379be5ed7da3f2688d0d1de0d42
https://doi.org/10.1007/978-3-030-50533-2_9
https://doi.org/10.1007/978-3-030-50533-2_9
Publikováno v:
ISOCC
In this paper, we propose a 32-bit processor for the embedded system. In order to provide less area and low power operation, we adopt MIPS instruction set architecture (ISA) to our processor. The processor consists of five pipeline stages to reduce t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5b88d2d8fd4dd1dec5fbe0f5aa77b0d
https://doi.org/10.1109/isocc50952.2020.9332944
https://doi.org/10.1109/isocc50952.2020.9332944
Autor:
Mong Tee Sim, Qing Yi
Publikováno v:
2020 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS).
Low power consumption, high performance, and small die size are the three essential considerations in modern CPU design, from tiny IoT devices to General Purpose Manycore System-on-Chip. With these considerations, we introduce a new CPU design that f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f91d7ba9e1b889a99ace5fdcc3aa918
https://doi.org/10.1109/iemtronics51293.2020.9216450
https://doi.org/10.1109/iemtronics51293.2020.9216450
Publikováno v:
DSD
A 40 MHz, 32-bit, 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic readmodify-write operations. The proposed system implements inorder issuing of in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8898936e542c10494a83105623e3da9
https://doi.org/10.1109/dsd51259.2020.00062
https://doi.org/10.1109/dsd51259.2020.00062
Autor:
Ankit Gupta, Angela Nicoara, Tanay Karnik, Mukesh Bhartiya, Krishnan Ravichandran, Saransh Chhabra, Kurian Dileep J, Jaykant B. Timbadiya, Saksham Soni, Kim Suhwan
Publikováno v:
ISQED
We present an end to end IoT system that works off harvested energy from multiple sources. It includes X86s compute, security and image inference at the edge. The mote is self-powered by an energy harvesting power management IC (EHPMIC). The system c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fcf845fb519ff91fba0df812e2b0ba0e
https://doi.org/10.1109/isqed48828.2020.9137027
https://doi.org/10.1109/isqed48828.2020.9137027
Publikováno v:
Advanced Information Networking and Applications ISBN: 9783030440404
AINA
AINA
Modern processors usually adopt pipeline structure and often load data from memory. At that point, the load-use hazard will inevitably occur, which usually stall the pipeline and reduce performance. This paper introduces and compares two schemes to s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b369df4c1212c99498d28b0c6772cd4a
https://doi.org/10.1007/978-3-030-44041-1_50
https://doi.org/10.1007/978-3-030-44041-1_50
Publikováno v:
ReConFig
With the increasing popularity of RISC-V in the academic and industrial world, an ever growing number of open-source implementations of the instruction set have become available. However, it is not an easy task to compare the cores to one another, as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95a37c9d83baf37c36bb28f606ee4148
https://doi.org/10.1109/reconfig48160.2019.8994796
https://doi.org/10.1109/reconfig48160.2019.8994796
Autor:
Qing Yi, Mong Tee Sim
Publikováno v:
2019 IEEE 5th International Conference on Computer and Communications (ICCC).
For CPUs, the design tradeoffs between high-performance computing and low-power consumption can be made a run-time decision instead of being statically built into each system. The ability to dynamically conFigure a system for either purpose, dependin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b39ab7ea16d0d422c1c973294f9de4e8
https://doi.org/10.1109/iccc47050.2019.9064185
https://doi.org/10.1109/iccc47050.2019.9064185
Autor:
Reoma Matsuo, Koji Inoue, Junichiro Kadomoto, Akifumi Fujita, Ryota Shioya, Toru Koizumi, Hidetsugu Irie, Masahiro Goshima, Seiya Akaki, Susumu Mashimo, Akifumi Fukuda
Publikováno v:
FPT
High-performance soft processors in field-programmable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack. An out-of-order (O
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6610f1ceb7fd7431a28af87dbe561aee
https://doi.org/10.1109/icfpt47387.2019.00016
https://doi.org/10.1109/icfpt47387.2019.00016