Testability strategy in production for printed circuit board assemblies with high density and high speed signals

Autor: El Belghiti Alaoui, Nabil

Publikováno v: Micro et nanotechnologies/Microélectronique. Institut National des Sciences Appliquées de Toulouse, 2020. Français
Micro et nanotechnologies/Microélectronique. INSA de Toulouse, 2020. Français. ⟨NNT : 2020ISAT0018⟩

Until today, the production tests are based mainly on optical verification (AOI), X-ray inspection (AXI), electrical (ICT) and functional tests. Faced with the miniaturization of component packages, the high densification and integration of several t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::1f01a5c765e10469dbf5aa187b88ce2c
https://hal.laas.fr/tel-03162010/document

Test planning and test access mechanism design for stacked chips using ILP

Autor: Breeta Sengupta, Erik Larsson

Publikováno v: VTS
pp 1-6 (2014)

In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1e90c311412eb25880e9094ca13ef941
https://doi.org/10.1109/vts.2014.6818764

Non-intrusif built-in sensors for RF circuit testing

Autor: Abdallah, Louay

Publikováno v: Autre. Université de Grenoble, 2012. Français. ⟨NNT : 2012GRENT104⟩

This thesis aims to study techniques such BIST for RF front-end, whereas new types of simple integrated sensors for signal extraction. These signals and stimuli associated test will then be processed by machine learning algorithms that will allow pre

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::923df526ff4f69aa86f60990576ec71b
https://tel.archives-ouvertes.fr/tel-01062479/document

Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias

Autor: Sengupta, Breeta, Ingelsson, Urban, Larsson, Erik

In this paper we have proposed a test cost model for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike in the case of non-stacked chips, where the test flow is well defined by applying the same test schedule both at wa

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::812312c74ac83804f15ea56445c832e1
https://lup.lub.lu.se/record/4302358

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