Zobrazeno 1 - 10
of 36
pro vyhledávání: '"Devos, Harald"'
Publikováno v:
Annual Workshop on Circuits, Systems and Signal Processing, 20th, Proceedings
Engineering of Reconfigurable Systems and Algorithms, Proceedings
Engineering of Reconfigurable Systems and Algorithms, Proceedings
This research explored different memory systems on FPGA chips in order to show the various trade-offs involved with choosing one memory system over another. We explored the different memory components that are found on FPGA chips using the example of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::db8e22e9788d30a54adf9e811356756a
https://hdl.handle.net/1854/LU-864518
https://hdl.handle.net/1854/LU-864518
Publikováno v:
International Conference on Design Automation and Test in Europe, Abstracts
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::3c1ee9fd51821cf2f9d2a16e86224242
https://hdl.handle.net/1854/LU-8701028
https://hdl.handle.net/1854/LU-8701028
Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this oc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::a9234a65b6a47258720c257bb6dde952
https://biblio.ugent.be/publication/679177
https://biblio.ugent.be/publication/679177
Autor:
Devos, Harald, Stroobandt, Dirk
Publikováno v:
DAC Workshop, 45th, Abstracts
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::31800640eb56799ddc9675a8cba2706d
https://biblio.ugent.be/publication/680842
https://biblio.ugent.be/publication/680842
Autor:
Devos, Harald
Current high-level design environments offer little support to implement data-intensive applications on heterogeneous-memory systems; they rather focus on parallelism. This thesis addresses the memory hierarchy problem to high-level transformations o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::245a0236f97f3643fef66c09fb61e8a7
https://biblio.ugent.be/publication/469156/file/4334587
https://biblio.ugent.be/publication/469156/file/4334587
The high potential performance of FPGAs cannot be exploited if a design suffers a memory bottleneck. Therefore, a memory hierarchy is needed to reuse data in on-chip memories and minimize the number of accesses to off-chip memory.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::6891a742a5ac3db62ed5f528296ee3cf
https://biblio.ugent.be/publication/679232
https://biblio.ugent.be/publication/679232
Publikováno v:
Architecture and Compilers for Embedded Systems (ACES 2007), Edegem. 2007
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::f0cc72c06f37e43ac084c480518331b5
https://biblio.ugent.be/publication/416816/file/448103
https://biblio.ugent.be/publication/416816/file/448103
In the context of the RESUME-project a scalable wavelet-based video decoder was built to demonstrate the benefits of reconfigurable hardware for scalable applications. emph{Scalable} video means that the quality of service (QoS), i.e., the frame rate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::272e09ccea26775f76c0245785ce1af8
Publikováno v:
Architecture and Compilers for Embedded Systems (ACES 2007), Ghent
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::b8227783eb21c454daaa8eaa79eef523
https://hdl.handle.net/1854/LU-416982
https://hdl.handle.net/1854/LU-416982
Publikováno v:
DATE 2007 University Booth, Nice, France. 2007
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______330::e3296529f7eb520d04f1193866438b21
https://biblio.ugent.be/publication/416628
https://biblio.ugent.be/publication/416628