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pro vyhledávání: '"Devi, J. Dhurga"'
This paper deals with the study of the impact of power supply noise on the performance of CMOS Clock and Data Recovery (CDR) Circuits. The sensitivity of the various blocks of the dual loop CDR circuit to power supply noise is first studied and then
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______4486::2939b0858ff9cf1430762db67ff6cb5f
https://hdl.handle.net/20.500.12415/5986
https://hdl.handle.net/20.500.12415/5986
Publikováno v:
International Conference on Circuits, Communication, Control & Computing; 2014, p37-40, 4p
Publikováno v:
International Conference on Circuits, Communication, Control & Computing; 2014, p29-32, 4p
Publikováno v:
International Journal of Design, Analysis & Tools for Integrated Circuits & Systems; 2011, Vol. 1 Issue 1, p16-21, 6p