Zobrazeno 1 - 10
of 72
pro vyhledávání: '"Deterministic testing"'
Autor:
Roei Tell
Publikováno v:
computational complexity. 28:259-343
This work studies the question of quantified derandomization, which was introduced by Goldreich and Wigderson (STOC 2014). The generic quantified derandomization problem is the following: For a circuit class $${\mathcal{C}}$$ and a parameter B=B(n),
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e836723daa688499dbb501711dcaa608
https://doi.org/10.1007/s00037-019-00179-2
https://doi.org/10.1007/s00037-019-00179-2
Autor:
Wu-Tung Cheng, Sudhakar M. Reddy, Fong-Jyun Tsai, Kuen-Jong Lee, Yu Huang, Mark Kassab, Chong-Siao Ye, Janusz Rajski
Publikováno v:
ETS
A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be signific
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6984c43b2b4c8a1fca6d8d9a6ce20b1
https://doi.org/10.1109/ets48528.2020.9131586
https://doi.org/10.1109/ets48528.2020.9131586
Autor:
Tsutomu Inamoto, Yoshinobu Higami
Publikováno v:
2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).
This study displays preliminary results on a simple technique to improve fault coverages in the BIST technology. The technique assumes that a circuit which implements an ANN can be used with the target circuit, and effective test patterns are given b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4682613af92c4a002dac26e4f11628f
https://doi.org/10.1109/itc-cscc.2019.8793374
https://doi.org/10.1109/itc-cscc.2019.8793374
Autor:
Tománek, Jakub
This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two
Externí odkaz:
http://www.nusl.cz/ntk/nusl-320175
Publikováno v:
International Journal of Digital Content Technology and its Applications. 4:88-96
As the number of specified bits of different test patterns varies widely in a deterministic test cube, all test patterns are concatenated to a data flow. The original test data can be re-divided by 2 to the power of integer according to the successfu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7616c226bd2674e542052a16c3abe953
https://doi.org/10.4156/jdcta.vol4.issue9.11
https://doi.org/10.4156/jdcta.vol4.issue9.11
Publikováno v:
Journal of Electronic Testing. 26:443-451
In this work, a new method to design a mixed-mode Test Pattern Generator (TPG) based only on a simple and single Linear Feedback Shift Register (LFSR) is described. Such an LFSR is synthesized by Berlekamp---Massey algorithm (BMA) and is capable of g
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10223b6654c8eb46e0850e973e6bc14b
https://doi.org/10.1007/s10836-010-5155-x
https://doi.org/10.1007/s10836-010-5155-x
Autor:
Irith Pomeranz, Sudhakar M. Reddy
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17:45-54
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We investigate a complementary view whereby the goal is to avoid the assignment of certain input values in order not to prevent faults from
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a6657cb3c6c5dea582acd111bccd879
https://doi.org/10.1109/tvlsi.2008.2001943
https://doi.org/10.1109/tvlsi.2008.2001943
Autor:
Dongsup Song, Sungho Kang
Publikováno v:
IEICE Transactions on Information and Systems. :354-357
In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST that can improve the embedding probabilities of random-pattern-resistant-patterns. A simulated annealing based algorithm that maximizes the embedding probabilit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c69cc076c28c625fa5705bb373c0b4c
https://doi.org/10.1093/ietisy/e89-d.1.354
https://doi.org/10.1093/ietisy/e89-d.1.354
Autor:
Nur A. Touba, K.J. Balakrishnan
Publikováno v:
Journal of Systems Architecture. 50:247-256
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::951e1ed51f8d43a5a062d9af5c328644
https://doi.org/10.1016/j.sysarc.2003.08.007
https://doi.org/10.1016/j.sysarc.2003.08.007