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pro vyhledávání: '"Derrien , Steven"'
Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on reducing of off-chip transfers, but few authors try to improve the effic
Externí odkaz:
http://arxiv.org/abs/2401.12071
Optimization pipelines targeting polyhedral programs try to maximize the compute throughput. Traditional approaches favor reuse and temporal locality; while the communicated volume can be low, failure to optimize spatial locality may cause a low I/O
Externí odkaz:
http://arxiv.org/abs/2312.03646
Programs admitting a polyhedral representation can be transformed in many ways for locality and parallelism, notably loop tiling. Data flow analysis can then compute dependence relations between iterations and between tiles. When tiling is applied, c
Externí odkaz:
http://arxiv.org/abs/2211.15933
Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the accelerator's effect
Externí odkaz:
http://arxiv.org/abs/2202.05933
Akademický článek
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Autor:
Abbas, Naeem, Derrien, Steven, Rajopadhye, Sanjay, Quinton, Patrice, Cornu, Alexandre, Lavenier, Dominique
Publikováno v:
In Microprocessors and Microsystems October 2015 39(7):457-470
Publikováno v:
2022 International Conference on Field-Programmable Technology (ICFPT)
FPT 2022-International Conference on Field Programmable Technology
FPT 2022-International Conference on Field Programmable Technology, Dec 2022, Honk Kong / Hybrid, Hong Kong SAR China. pp.1-6, ⟨10.1109/ICFPT56656.2022.9974478⟩
FPT 2022-International Conference on Field Programmable Technology
FPT 2022-International Conference on Field Programmable Technology, Dec 2022, Honk Kong / Hybrid, Hong Kong SAR China. pp.1-6, ⟨10.1109/ICFPT56656.2022.9974478⟩
International audience; The RISC-V ecosystem is quickly growing and has gained a lot of traction in the FPGA community, as it permits free customization of both ISA and microarchitectural features. However, the design of the corresponding micro-archi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::480ef1bc73a2a9df7bd7b964ac602b88
https://inria.hal.science/hal-03828841
https://inria.hal.science/hal-03828841
Akademický článek
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Autor:
Stripf, Timo, Oey, Oliver, Bruckschloegl, Thomas, Becker, Juergen, Rauwerda, Gerard, Sunesen, Kim, Goulas, George, Alefragis, Panayiotis, Voros, Nikolaos S., Derrien, Steven, Sentieys, Olivier, Kavvadias, Nikolaos, Dimitroulakos, Grigoris, Masselos, Kostas, Kritharidis, Dimitrios, Mitas, Nikolaos, Perschke, Thomas
Publikováno v:
In Microprocessors and Microsystems November 2013 37(8) Part C:1033-1049