Zobrazeno 1 - 10
of 82
pro vyhledávání: '"Derek Chiou"'
Autor:
Tian Tan, Rajesh Vivekanandham, Derek Chiou, Eriko Nurvitadhi, Jia-Ching Hsu, Rui Ma, Aravind Dasu, Martin Langhammer
Publikováno v:
FPL
”Soft” GPUs are overlays that implement GPGPU-like data parallel processor architectures in FPGA logic to make FPGAs as software-programmable as ”hard” GPGPUs. Unlike hard GPUs, soft GPU architectures can be specialized to further improve eff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e30b3ea4b75f104bd99853bc19b5d8e
https://doi.org/10.1109/fpl53798.2021.00031
https://doi.org/10.1109/fpl53798.2021.00031
Autor:
Ming Wu, Dechen Zhan, Ramashis Das, Lanshun Nie, Derek Chiou, Lintao Zhang, Shijie Cao, Ningyi Xu, Wenqiang Wang
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 12:1-20
Web search engines deploy large-scale selection services on CPUs to identify a set of web pages that match user queries. An FPGA-based accelerator can exploit various levels of parallelism and provide a lower latency, higher throughput, more energy-e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02dbfe4598aeccca68058ed66e552f14
https://doi.org/10.1145/3301409
https://doi.org/10.1145/3301409
Publikováno v:
IEEE Computer Architecture Letters. 18:67-70
Power has become a fundamental limit to silicon performance. Most research has focused on reducing transistor switching to constrain power (dark silicon.) Specialized accelerators have been proposed since they implement functionality with fewer trans
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82fc78b722ccb14aef2c9cbc82e41d8e
https://doi.org/10.1109/lca.2019.2909867
https://doi.org/10.1109/lca.2019.2909867
Publikováno v:
ASPLOS
The importance of irregular applications such as graph analytics is rapidly growing with the rise of Big Data. However, parallel graph workloads tend to perform poorly on general-purpose chip multiprocessors (CMPs) due to poor cache locality, low com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7cb9c7af8fa28c4678ba6cd54ae6440f
https://doi.org/10.1145/3296957.3173197
https://doi.org/10.1145/3296957.3173197
Autor:
Friedel van Megen, Oren Firestein, Bita Darvish Rouhani, Mahdi Ghandi, Christian Boehn, Prerak Patel, Kara Kagi, Hari Angepat, Doug Burger, Brandon Perez, Raja Seera, Tamas Juhasz, Jeremy Fowers, Shlomi Alkalay, Logan Adams, Gabriel Weisz, Balaji Sridharan, Sangeetha Shekar, Kyle Holohan, Ritchie Zhao, Amanda Rapsang, Ahmad M. El Husseini, Adam Sapek, Todd Massengill, Kalin Ovtcharov, Sitaram Lanka, Dan Zhang, Michael K. Papamichael, Derek Chiou, Lo Daniel, Michael Haselman, Lisa Woods, Kang Su Gatlin, Maleen Abeydeera, Phillip Yi Xiao, Steven K. Reinhardt, Adrian M. Caulfield, Eric S. Chung, Alessandro Forin, Stephen F. Heil, Ratna Kumar Kovvuri, Dima Mukhortov, Ming Liu
Publikováno v:
IEEE Micro. 38:8-20
To meet the computational demands required of deep learning, cloud operators are turning toward specialized hardware for improved efficiency and performance. Project Brainwave, Microsofts principal infrastructure for AI serving in real time, accelera
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06234ab71359683ab5a29f25bae89139
https://doi.org/10.1109/mm.2018.022071131
https://doi.org/10.1109/mm.2018.022071131
To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field
Publikováno v:
IEEE Computer Architecture Letters. 16:170-173
Researchers have demonstrated the benefits of hardware worklist accelerators, which offload scheduling and load balancing operations in parallel graph applications. However, many of these applications are still heavily memory latency-bound due to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a3ef9b549c19a0a25377d755a0716cf
https://doi.org/10.1109/lca.2016.2627571
https://doi.org/10.1109/lca.2016.2627571
Autor:
Hari Angepat, Eric S. Chung, Stephen F. Heil, Todd Massengill, Doug Burger, Matt Humphrey, Joo-Young Kim, Andrew Putnam, Adrian M. Caulfield, Derek Chiou, Lisa Woods, Jeremy Fowers, Sitaram Lanka, Daniel Firestone, Puneet Kaur, Kalin Ovtcharov, Lo Daniel, Michael K. Papamichael, Michael Haselman
Publikováno v:
IEEE Micro. 37:52-61
Hyperscale datacenter providers have struggled to balance the growing need for specialized hardware with the economic benefits of homogeneity. The Configurable Cloud datacenter architecture introduces a layer of reconfigurable logic (FPGAs) between t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae14977a8c204605023cd612c028b386
https://doi.org/10.1109/mm.2017.51
https://doi.org/10.1109/mm.2017.51
Publikováno v:
FPT
Intel Stratix 10 FPGAs offer a novel architectural feature called HyperFlex that enables an extreme degree of pipelining resulting in up to 1GHz clock frequencies. Prior work has evaluated HyperFlex on pre-production Stratix 10 FPGAs using internal d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5b750381058a7a726e032daeba0d444
https://doi.org/10.1109/fpt.2018.00038
https://doi.org/10.1109/fpt.2018.00038