Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Dennis J.-H. Huang"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42:164-177
Autor:
Charles J. Alpert, Dennis J.-H. Huang, Tony F. Chan, Igor L. Markov, Andrew Caldwell, M. S. Moroz, Andrew B. Kahng
Publikováno v:
VLSI Design, Vol 10, Iss 1, Pp 99-116 (1999)
The top-down “quadratic placement” methodology is rooted in such works as [36, 9, 32] and is reputedly the basis of commercial and in-house VLSI placement tools. This methodology iterates between two basic steps: solving sparse systems of linear
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16:1199-1205
Iterative improvement partitioning algorithms such as the FM algorithm of Fiduccia and Mattheyses (1982), the algorithm of Krishnamurthy (1984), and Sanchis's extensions of these algorithms to multiway partitioning (1989) all rely on efficient data s
Publikováno v:
DAC
Hong Kong University of Science and Technology
Hong Kong University of Science and Technology
The "quadratic placement" methodology is rooted in [Module Placement Based on Resistive Network Optimization, Proud: A Sea-Of-Gate Placement Algorithm, A Combined Force and Cut Algorithm for Hierarchical VLSI Layout]and is reputedly used in many comm
Autor:
Dennis J.-H. Huang, Andrew B. Kahng
Publikováno v:
ISPD
We present a new top-down quadrisection-based global placer for standard-cell layout. The key contribution is a new general gain update scheme for partitioning that can exactly capture detailed placement objectives on a per-net basis. We use this gai
Autor:
null Dennis J.-H. Huang
Publikováno v:
32nd Design Automation Conference.
Publikováno v:
DAC
We study theminimum-cost bounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For
Publikováno v:
DAC
We show how to quantify the suboptimality of heuristic algorithms for NP-hard problems arising in VLSI layout. Our approach is based on the notion of constructing new scaled instances from an initial problem instance. From the given problem instance,
Autor:
Igor L. Markov, Pep Mulet, Kenneth Yan, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Charles J. Alpert
Publikováno v:
Hong Kong University of Science and Technology
ISPD
ISPD
A linear wirelength objective more effectively cap- tures timing, congestion, and other global placement considera- tions than a squared wirelength objective. The GORDIAN-L cell placement tool (19) minimizes linear wirelength by first approx- imating
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8649f205155313b58687978fd0dd2472
http://hdl.handle.net/1783.1/48468
http://hdl.handle.net/1783.1/48468
Conference
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