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pro vyhledávání: '"Dennis Crippa"'
Publikováno v:
IOLTS
A radiation hardened flip-flop immune to soft errors is proposed which is based on robust differential input latches working on single-phase clock. The proposed circuit is implemented in 90nm ST BCD process and is found to have lower power consumptio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6491fdbbfddeae4093472480fcf2ccef
http://hdl.handle.net/11577/3365374
http://hdl.handle.net/11577/3365374
Autor:
Dennis Crippa, Abhishek Jain, Andrea Veggetti, Simone Gerardin, A. Castelnovo, Carlo Cazzaniga, S. Garg, A. Gupta, Marta Bagatin
Publikováno v:
TENCON 2017 - 2017 IEEE Region 10 Conference.
A new radiation hardened flip-flop, named low power single-phase clocked rad-hard flip flop, is proposed. The structure is based on robust differential-input latches working on a single-phase clock, which allows a reduction in the number of nodes sen
Publikováno v:
European Test Symposium
A novel On-chip delay measurement circuit is presented which is suitable for wide applications involving on-chip measurements, monitoring and process compensation. The circuit is based upon multiple characterization units consisting of ring oscillato
Publikováno v:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation ISBN: 9783642177514
PATMOS
PATMOS
The performance of the sequential digital circuit (Speed, Power consumption etc.) depends upon the performance of flip-flop used in the design. ASIC design flows use characterized data of flip-flops for final signoff. Therefore it's critical to know
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd904c69bd92a97990687b687bd6fee0
https://doi.org/10.1007/978-3-642-17752-1_5
https://doi.org/10.1007/978-3-642-17752-1_5
Autor:
Fady Abouzeid, Sylvain Clerc, Abhishek Jain, Gilles Sicard, Philippe Roche, Dennis Crippa, Andrea Veggetti, Vincent Heinrich
Publikováno v:
Proc. of IEEE International Conference on Integrated Circuit Design and Technology (ICICDT'10)
IEEE International Conference on Integrated Circuit Design and Technology (ICICDT'10)
IEEE International Conference on Integrated Circuit Design and Technology (ICICDT'10), Jun 2010, Grenoble, France. pp.78-81, ⟨10.1109/ICICDT.2010.5510284⟩
IEEE International Conference on Integrated Circuit Design and Technology (ICICDT'10)
IEEE International Conference on Integrated Circuit Design and Technology (ICICDT'10), Jun 2010, Grenoble, France. pp.78-81, ⟨10.1109/ICICDT.2010.5510284⟩
ISBN 978-1-4244-5773-1; International audience; Following the will to answer to the energy constrained applications requirements, an Ultra-Low Voltage (ULV) 40nm Bose-Chaudhuri-Hocquenghem (BCH) error-correcting circuit is presented. Mapped on a ULV