Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Denis Amparo"'
Publikováno v:
IEEE Transactions on Applied Superconductivity. 29:1-9
As superconducting circuits grow in complexity, full transient simulation and verification at the Josephson junction level using analog circuit simulators become increasingly computationally expensive. To enable faster functional and timing verificat
Publikováno v:
IEEE Transactions on Applied Superconductivity. 29:1-7
A test structure suite to measure circuit delays, power, and operating margins of single flux quantum (SFQ) circuits and to derive key parameters directly from dc testable high-speed circuits is described. This suite comprises a set of ring oscillato
Autor:
Oleg A. Mukhanov, Igor V. Vernik, Anubhav Sahu, M. Y. Kamkar, C. Shawawreh, Alex F. Kirichenko, Denis Amparo, A. Inamdar, M. Miller, Jie Ren
Publikováno v:
IEEE Transactions on Applied Superconductivity. 27:1-6
Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeof
Autor:
Rick T. Hunt, Alex F. Kirichenko, Igor V. Vernik, Alexander Cohen, Daniel Yohannes, John Vivalda, Denis Amparo
Publikováno v:
IEEE Transactions on Applied Superconductivity. 25:1-5
We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE
Publikováno v:
IEEE Transactions on Applied Superconductivity. 25:1-8
Superconductor (SC) integrated circuits have several inherent advantages including low power, high speed, and fractional flux quantum sensitivity that can be exploited to achieve discriminating performance for several niche applications in the high-s
Autor:
T.V. Filippov, M. Y. Kamkar, Jason Walter, Igor V. Vernik, O.A. Mukhanov, Denis Amparo, Alex F. Kirichenko
Publikováno v:
2017 16th International Superconductive Electronics Conference (ISEC).
We present test results for parallel data communication ERSFQ circuits with clock recovery. We experimentally study on-chip and chip-to-chip parallel data communication circuits with 4-, 8- and 16-bit word lengths. The largest circuit is a 16-bit chi
Publikováno v:
IEEE Transactions on Applied Superconductivity. 21:119-125
New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting
Autor:
Sergey K. Tolpygo, Denis Amparo
Publikováno v:
IEEE Transactions on Applied Superconductivity. 21:126-130
The correct operation and high performance of complex superconducting integrated circuits significantly depend on fabrication-process-induced variations of the Josephson junction critical current Ic. Such variations in Nb/Al/AlOx/Nb junctions were in
Publikováno v:
IEEE Transactions on Applied Superconductivity. 19:135-139
It is shown that the critical current density, jc of Nb/AlOx/Nb Josephson junctions in multilayered structures such as superconductor integrated circuits depends on the junction environment and on which wiring layers make contacts to the junction ele
Autor:
Denis Amparo, Sergey K. Tolpygo
Publikováno v:
IEEE Transactions on Applied Superconductivity. 19:154-158
Fabrication-induced variations in the critical currents of Josephson junctions significantly affect the performance and yield of complex superconducting integrated circuits. Electrical stress that may develop during plasma processing steps in the fab