Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Dengquan Li"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:1558-1562
Publikováno v:
IEEE Sensors Journal. 22:17904-17913
Publikováno v:
Circuits, Systems, and Signal Processing. 41:6632-6650
Autor:
Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu
Publikováno v:
2023 IEEE Custom Integrated Circuits Conference (CICC).
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:2672-2676
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 69:1091-1101
In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined
Publikováno v:
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA).
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:888-892
A high-speed time domain analog-to-digital converter (ADC) customized for impulse radio ultra-wideband (IR-UWB) radars is proposed in this brief. It adopts a power efficient architecture combining time domain implementation and equivalent sampling te
Publikováno v:
IEEE Sensors Journal. 20:13881-13891
This paper introduces a low-power noise-shaping SAR ADC which is suitable for biomedical sensor applications. In this ADC, a low power consumption and area-efficient integrator is proposed, which is comprised of several switches, replica capacitors a
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:2307-2311
This brief presents an 8-bit 350-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 1.5 b/cycle redundancy in 65-nm CMOS. With 12.5% redundancy in conversion cycles, conversion errors caused by capacitor mismatch, off