Výsledky vyhledávání - "Denais, Mickael"

Dissertation/ Thesis

ETUDE DES PHENOMENES DE DEGRADATION DE TYPENEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI)DANS LES TRANSISTORS MOS SUBMICRONIQUES DESFILIERES CMOS AVANCEES

Autor: Denais, Mickael

La miniaturisation croissante des circuits intégrés entraîne une augmentation de la complexité des procédés defabrication où chaque nouvelle étape peut influer la fiabilité du composant. Les fabricants de semi-conducteursdoivent garantir un

Externí odkaz: http://tel.archives-ouvertes.fr/tel-00011973
http://tel.archives-ouvertes.fr/docs/00/06/30/17/PDF/DENAIS_these.pdf

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Negative-Bias Temperature Instability (NBTI) degradation phenomena in advanced CMOS technologies' submicron devices

Autor: Denais, Mickael

Publikováno v: Analyse de données, Statistiques et Probabilités [physics.data-an]. Université de Provence-Aix-Marseille I, 2005. Français
Analyse de données, Statistiques et Probabilités [physics.data-an]. Université de Provence-Aix-Marseille I, 2005. Français. ⟨NNT : ⟩

CMOS transistor scaling-down involves an increase in the manufacturing complexity and brings up reliability as a serious challenge to overcome in recent node technologies. In this context, it is mandatory to characterize and model the various failure

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::4d63d8dbbd1701c491ebe9276a95dc8e
https://tel.archives-ouvertes.fr/tel-00011973

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation:: 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings

Autor: Parthasarathy, Chittoor, Bravaix, Alain, Guérin, Chloé, Denais, Mickael, Huard, Vincent

Publikováno v: 17th International Workshop, PATMOS 2007
17th International Workshop, PATMOS 2007, Sep 2007, Goteborg Sweden, France. pp.191-200

International audience; Practical and accurate Design-in Reliability methodology has been developedfor designs on 90-45nm technology to quantitatively assess the degradationdue to Hot Carrier and Negative Bias Temperature Instability. Simulationcapab

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______3430::afffd335af7898b6619cbbbb30477570
https://hal.science/hal-03660397

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Autor: Parthasarathy, Chittoor, Bravaix, Alain, Guérin, Chloé, Denais, Mickael, Huard, Vincent

Practical and accurate Design-in Reliability methodology has been developedfor designs on 90-45nm technology to quantitatively assess the degradationdue to Hot Carrier and Negative Bias Temperature Instability. Simulationcapability has been built on

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od_______166::afffd335af7898b6619cbbbb30477570
https://hal.science/hal-03660397

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