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pro vyhledávání: '"Deepesh Gujjar"'
Publikováno v:
VLSI Design
The paper presents SRAM cache design in 5nm FinFET technology for L2/L3 cache applications, demonstrating circuit techniques to enable wide-range DVFS (Dynamic Voltage and Frequency scaling) operation. CPU L2/L3 SRAM cache must achieve higher density
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c218aa82b6bb1628d8f378f95db7abd8
https://doi.org/10.1109/vlsid51830.2021.00031
https://doi.org/10.1109/vlsid51830.2021.00031
