Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Deepak M. Mathew"'
Publikováno v:
IEEE Access, Vol 9, Pp 83950-83962 (2021)
Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental
Externí odkaz:
https://doaj.org/article/d56cd327e0574c26a0c37456501f8968
Autor:
Muhammad Mohsin Ghaffar, Éder F. Zulian, Felipe S. Prado, Norbert Wehn, Deepak M. Mathew, Christian Weis, Matthias Jung
Publikováno v:
MEMSYS
The demand for main memory capacity is ever increasing in mobile devices and embedded systems. Dynamic Random Access Memories (DRAMs) can not keep pace with the required main memory capacities because of the restrictions in improving the cell density
Publikováno v:
IEEE Design & Test. 34:52-59
Editor’s note: The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability. Their unique platform allows tailoring to the design constraints depending on whether power consumption, perfor
Autor:
Matthias Jung, Christian Weis, Pascal Vivet, Norbert Wehn, Deepak M. Mathew, Bastien Giraud, Alexandre Levisse, André Lucas Chinazzo
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783030275617
SAMOS
Embedded Computer Systems: Architectures, Modeling, and Simulation-19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings
Lecture Notes in Computer Science
Lecture Notes in Computer Science-Embedded Computer Systems: Architectures, Modeling, and Simulation
SAMOS
Embedded Computer Systems: Architectures, Modeling, and Simulation-19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings
Lecture Notes in Computer Science
Lecture Notes in Computer Science-Embedded Computer Systems: Architectures, Modeling, and Simulation
Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate archite
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e7148722fab265061457fa9a3bbcc6c9
https://doi.org/10.1007/978-3-030-27562-4_3
https://doi.org/10.1007/978-3-030-27562-4_3
Publikováno v:
DATE
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
In this paper, we present a new communication theoretic channel model for Dynamic Random Access Memory (DRAM) retention errors, that relies on the fully asymmetric retention error behavior of DRAM cells. This new model shows that the traditional appr
Autor:
Norbert Wehn, Christian Weis, Martin Schultheis, Carl C. Rheinlander, Matthias Jung, Deepak M. Mathew, Chirag Sudarshan
Publikováno v:
DATE
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
DRAM technology is scaling aggressively that results in high leakage power, worse data retention time behavior, and large process variations. Due to these process variations, vendors provide large guard bands on various DRAM currents and timing speci
Autor:
Christian Weis, Deepak M. Mathew, Norbert Wehn, Matthias Jung, Éder F. Zulian, Subash Kannoth
Publikováno v:
RAPIDO
DRAM devices contribute significantly to the power consumption of today's computing systems. As the DRAM banks are getting denser, bank-wise power contribution is becoming more and more significant in modern DRAM devices. Therefore, DDR3 and LPDDR3/4
Autor:
Deepak M. Mathew, Bruce Jacob, Christian Weis, Kira Kraft, Norbert Wehn, Matthias Jung, Éder F. Zulian
Publikováno v:
Proceedings of the International Symposium on Memory Systems -MEMSYS '17
Proceedings of the International Symposium on Memory Systems-MEMSYS 17
MEMSYS
Proceedings of the International Symposium on Memory Systems
Proceedings of the International Symposium on Memory Systems-MEMSYS 17
MEMSYS
Proceedings of the International Symposium on Memory Systems
The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates th
Autor:
Marco V. Natale, Sven O. Krumke, Christian Weis, Deepak M. Mathew, Norbert Wehn, Irene Heinrich, Matthias Jung
Publikováno v:
MEMSYS
The increasing gap between the bandwidth requirements of modern Systems on Chip (SoC) and the I/O data rate delivered by Dynamic Random Access Memory (DRAM), known as the Memory Wall, limits the performance of today's data-intensive applications. Gen
Publikováno v:
PATMOS
In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a large impact on performance and contribute a significant part to the total consumed power. Therefore, it is crucial to have an accurate DRAM power model f