Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Davide Ponton"'
Publikováno v:
ICECS
This paper presents a DPA design with a DAT power combiner drawn in the package metallization achieving 26.7dBm maximum output power at 25% PAE using 0.5mm2 area on die and 0.5mm2 on package. Thanks to an offline static 2D DPD, an EVM as low as 4.1%a
Publikováno v:
Analog Integrated Circuits and Signal Processing. 89:307-315
This paper presents the design of a matching network (MN) for switched-capacitor PAs (SCPA) optimized for efficiency against required load output power. The presented third-order MN exploits the intrinsic output capacitance of the SCPA, reducing the
Autor:
Zdravko Boos, Thomas Hartig, Stephan Leuschner, Ulrich Steinacker, Franz Kuttner, Alan Paussa, Jonas Fritzin, Daniel Sira, Thomas Maletz, Daniel Gruber, Davide Ponton, José E. Moreira, Vahur Kampus, Marcus Groinig, Nenad Stevanovic, Michael Fulde, Hans Geltinger, Boris Kapfelsberger, Harald Pretl, Andreas Menkhoff, Alexander Belitzer, Simon Gruenberger, Michael Bruennert
Publikováno v:
ISSCC
The evolving trend for increasing data rates in cellular communication systems with limited and fragmented frequency spectrum requires enhanced spectral efficiency of today's and future communication standards. The resulting need for high-order modul
Autor:
Edwin Thaller, Davide Ponton, Gerhard Knoblinger, Antonio Passamani, Andrea Bevilacqua, Andrea Neviani
Publikováno v:
ISSCC
In today's connected world, smaller and leaner wireless applications emerge, calling for increasingly higher integration and smaller footprint, while ensuring high reliability and operation at limited supply voltages. In this context, the integration
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::33b0b5283295f56303965a85fc7c9857
http://hdl.handle.net/11577/3227620
http://hdl.handle.net/11577/3227620
Autor:
Federico Cernoia, Peter Thurner, Davide Ponton, Pierpaolo Palestri, Giulio Cecco, Luca Selmi, Nicola Da Dalt
Publikováno v:
International Journal of Circuit Theory and Applications. 43:709-721
This paper presents the design and implementation of dual-band LC-VCOs in the GHz-range featuring a switched coil LC-tank. The proposed design exploits the self-inductance technique. The design of the coil starts from simple considerations and back-o
Publikováno v:
ESSCIRC
A circuit architecture to generate differential CMOS quadrature (I/Q) local oscillator (LO) signals from a differential input at the same frequency is presented. The phase accuracy of the proposed architecture relies on the matching of two delays and
Autor:
G. Knoblinger, Pierpaolo Palestri, A. Roithmeier, Michael Fulde, F. Cernoia, Davide Ponton, M. Tiebout
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 58:467-471
In this brief, a conventional LC voltage-controlled oscillator (LC-VCO) for Global System for Mobile Communications 900 applications is implemented in a 32-nm CMOS technology. The transition to 32-nm technology represents a big step from the technolo
Publikováno v:
NORCAS
A Matching Network for a 1.1V Switched Capacitor Power Amplifier has been designed with a Bluetooth Application in mind. The Matching Network has been implemented in a 28nm CMOS RF Metal Stack and provides 16.7dBm output power with IL = 1.1dB at 2.4G
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b978884c9f8add25b20be2d294a54335
http://hdl.handle.net/11577/3189841
http://hdl.handle.net/11577/3189841
Publikováno v:
2010 International Conference on Microelectronics.
This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm
Autor:
D. Siprak, G. Knoblinger, M. Tiebout, Davide Ponton, David Esseni, Bertrand Parvais, Pierpaolo Palestri, Luca Selmi
This paper deals with the design of single-stage differential low-noise amplifiers for ultra-wideband (UWB) applications, comparing state-of-the-art planar bulk and silicon-on-insulator (SOI) FinFET CMOS technologies featuring 45-nm gate length. To e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f2ec8e03c86629d2dbf3d48cbf8f81e4
https://hdl.handle.net/11380/1163248
https://hdl.handle.net/11380/1163248