Zobrazeno 1 - 10
of 16
pro vyhledávání: '"David Zaretsky"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:1177-1190
As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hard
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72eb7325e623f11a62497ceb49305ca7
https://doi.org/10.1109/tvlsi.2007.904095
https://doi.org/10.1109/tvlsi.2007.904095
Autor:
V. Kim, Vikram Saxena, Malay Haldar, David Zaretsky, R. Anderson, Prithviraj Banerjee, J.R. Uribe, Satrajit Pal, Nimisha Tripathi, S. Parkes, Anshuman Nayak, Debabrata Bagchi
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12:312-324
This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7a234d2842bd8ef08177db7a207898b
https://doi.org/10.1109/tvlsi.2004.824301
https://doi.org/10.1109/tvlsi.2004.824301
Publikováno v:
AHS
This paper presents a methodology for generating streaming architectures from ordinary programs. It automatically identifies streaming relationships and translates them into parallel computational kernels connected with customized stream buffers. New
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ac9bd26b457181a08660e092596f9c5
https://doi.org/10.1109/ahs.2011.5963928
https://doi.org/10.1109/ahs.2011.5963928
Publikováno v:
ICPP
We describe a novel approach for automatically generating streaming architectures from software programs. While existing systems require user-defined stream models, our method automatically identifies producer-consumer streaming relationships and tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b5bbee6d7743af17aa27638fe6950b9
https://doi.org/10.1109/icpp.2010.38
https://doi.org/10.1109/icpp.2010.38
Publikováno v:
ISCAS
Many new real-time system require high-speed compression and decompression solutions that provide low latency links between systems over a network interface. We describe a methodology for implementing an optimized streaming ZLIB decoder system on a X
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7fe41f89c9329c9ea8279653dcd86b16
https://doi.org/10.1109/iscas.2009.5118266
https://doi.org/10.1109/iscas.2009.5118266
Publikováno v:
ISCAS
With the proliferation of reconfigurable systems and flexible memory architectures, there has been intense interest in stream systems. While the existing stream systems require the programs to be written using special models, this paper demonstrates
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c592b88f142546d7f4d85f29fb4b2253
https://doi.org/10.1109/iscas.2009.5118053
https://doi.org/10.1109/iscas.2009.5118053
Publikováno v:
ISQED
In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb20373379dea62f24abf4b00abf65f1
https://doi.org/10.1109/isqed.2009.4810311
https://doi.org/10.1109/isqed.2009.4810311
Publikováno v:
FPGA
This paper describes an FPGA based implementation of a real time compression algorithm used in transactions between financial institutions such as exchanges and trading houses. FIX is a protocol that has gained widespread popularity for exchanging fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89a8c49adf25313b232a031718d80480
https://doi.org/10.1145/1508128.1508195
https://doi.org/10.1145/1508128.1508195
Publikováno v:
ISQED
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced scheduling routine that uniformly distributes operations across states to reduce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b78624396f0c9b9dd9880e6454cc3fd
https://doi.org/10.1109/isqed.2007.41
https://doi.org/10.1109/isqed.2007.41
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783540693291
LCPC
LCPC
High-level synthesis tools generally convert abstract designs described in a high-level language into a control and data flow graph (CDFG), which is then optimized and mapped to hardware. However, there has been little work on generating CDFGs from h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2046cd2a4bbcb5f8b42d27cee33795c8
https://doi.org/10.1007/978-3-540-69330-7_6
https://doi.org/10.1007/978-3-540-69330-7_6
