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pro vyhledávání: '"David Victor Pietromonaco"'
Publikováno v:
CICC
Compute demand has grown over 100X within the last decade and has well surpassed the growth in classical Moore’s Law transistor density (Fig. 1 (a) [1]). Plateaued dimension scaling even with fin depopulation, short channel effects and shrinking wi
Autor:
Vikas Chandra, Greg Yeric, David Victor Pietromonaco, Brian Cline, Saurabh Sinha, Shidhartha Das, Robert Campbell Aitken, Lucian Shifren
Publikováno v:
IET Computers & Digital Techniques. 10:315-322
Long timescales and complex design processes require that CPU architects and microarchitects have early access to information about future manufacturing processes. In some cases, this means that future technology must be predicted in advance of it ac
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
System-on-chip designs must take into account a large number of sources of variability in order to be manufacturable with suitable yield. Resilient design must begin with careful attention to these methods, but must also move beyond them. This paper
Publikováno v:
ICCD
For many years, a key aspect of Design-forManufacturability (DFM) has been adjustment of polygons in standard cell layout. Similarly, radically restricted design rules and unidirectional layout have been proposed as DFMfriendly design styles with the
Autor:
Greg Yeric, Robert Campbell Aitken, Vikas Chandra, Brian Cline, Saurabh Sinha, David Victor Pietromonaco
Publikováno v:
CICC
Design-Technology Co-Optimization (DTCO) has evolved from early Design-for-Manufacture (DFM) needs into a multi-faceted multi-lateral co-optimization below 20nm where multiple patterning and FinFETs add significant complexities. Effective DTCO now in
Publikováno v:
SPIE Proceedings.
When the technology node of logic devices is sub-14nm, finding lithographic solutions for most of the critical layers is challenging. For instance, metal 1 interconnect layer is one of the most lithographically difficult layers in a logic design, not
Autor:
Evelyn Mintarno, Robert W. Dutton, David Victor Pietromonaco, Vikas Chandra, Robert Campbell Aitken
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
This paper analyzes aging effects on various design hierarchies of a sub-45nm commercial processor running realistic applications. Dependencies of aging effects on switching-activity and power-state of workloads are quantified. This paper presents an
Publikováno v:
SPIE Proceedings.
Maintaining the microelectronics industry's aggressive pace of density scaling beyond the resolution limits of optical lithography is forcing the introduction of double-patterning technology (DPT) that effectively doubles the pattern density achievab