Zobrazeno 1 - 10 of 23 pro vyhledávání: '"David Turgis"'
1
1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off Applications
Autor: Jean-Philippe Noel, Reda Boumchedda, Edith Beigne, Pablo Royer, David Turgis, Christopher Mounet, Ivan Miro-Panades, Bastien Giraud, Jean-Frederic Christmann, A. Makosiej, Lorenzo Ciampolini
Publikováno v: IEEE Solid-State Circuits Letters. 1:186-189
This letter presents a single-rail two-port static random-access memory (SRAM) designed in 28-nm FD-SOI technology specifically for a synchronous/asynchronous Internet of Things node. This SRAM supports an asynchronous interface communication and a f
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::df10f8cb416c28110088f299351b0ccc
https://doi.org/10.1109/lssc.2019.2899971
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2
A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS
Autor: Anuj Grover, David Turgis, Ivan Miro-Panades, Shamsi Azmi, Bastien Giraud, Guillaume Moritz, G. S. Visweswaran, Chittoor Parthasarathy, Jean-Philippe Noel, Mohammad Daud, Promod Kumar, Edith Beigne, Philippe Flatresse
Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 64:2438-2447
An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35–1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential sup
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::caa40297e2b2f3bfcc75650e2d397f13
https://doi.org/10.1109/tcsi.2017.2705116
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3
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology
Autor: Jean-Philippe Noel, David Turgis, E. Esmanhotto, Marco Rios, R. Boumchedda, Edith Beigne, A. Makosiej, Emilien Bourde-Cice, Bastien Giraud, Mathis Bellet
Publikováno v: NANOARCH
This paper presents a 4T-based SRAM bitcell optimized both for write and read operations at ultra-low voltage (ULV). The proposed bitcell is designed to respond to the requirements of energy constrained systems, as in the case of most IoT-oriented ci
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1229f2490b66a757c6a2eeaa132cbc77
https://doi.org/10.1145/3232195.3232210
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4
Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28nm 3D CoolCubeTM Technology
Autor: David Turgis, E. Esmanhotto, Jean-Philippe Noel, Bastien Giraud, Emilien Bourde-Cice, Reda Boumchedda, Mathis Bellet, Marco Rios, Edith Beigne, Adam Makosiej
Publikováno v: EasyChair Preprints.
This paper presents a 4T-based SRAM bitcell optimized both for write and read operations at ultra-low voltage (ULV). The proposed bitcell is designed to respond to the requirements of energy constrained systems, as in the case of most of theIoT-orien
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::771e35968129cbce85ac59ac7a6e5ec2
https://doi.org/10.29007/nc31
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5
Sub-threshold 10T SRAM bit cell with read/write XY selection
Autor: Fady Abouzeid, Jean-Christophe Lafont, Sebastien Haendler, David Turgis, Anis Feki, Bruno Allard, Faress Tissafi Drissi
Publikováno v: Solid-State Electronics
Solid-State Electronics, Elsevier, 2015, 106, pp.1-11. ⟨10.1016/j.sse.2014.11.018⟩
International audience; New SRAM bit cell architectures have been proposed recently as solutions to the limitations of the six-transistor (6T) SRAM bit cell in term of minimum supply voltage, VDDMIN. There is no demonstrated bit cell as superior unde
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dee3287a8ea67d52f6d79283062b1050
https://doi.org/10.1016/j.sse.2014.11.018
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6
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques
Autor: Kaya Can Akyel, Bastien Giraud, Reda Boumchedda, M. Brocard, Edith Beigne, Jean-Philippe Noel, David Turgis
Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2017, 25 (8), pp.2296-2306. ⟨10.1109/TVLSI.2017.2688862⟩
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25 (8), pp.2296-2306. ⟨10.1109/TVLSI.2017.2688862⟩
International audience; In this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted-silicon on insulator MOS transistors to show th
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e8f8b5e9601d4d994015e4ccf7c1e997
https://hal-cea.archives-ouvertes.fr/cea-02193602
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7
Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells
Autor: Jean-Christophe Lafont, Faress Tissafi Drissi, Lorenzo Ciampolini, Xavier Jonsson, David Turgis, Jean-Paul Morin, Joseph Nguyen, Cyril Descleves
Publikováno v: ICCAD
We consider the general problem of the efficient and accurate determination of the yield of an integrated circuit, through electrical circuit level simulation, under variability constraints due to the manufacturing process. We demonstrate the perform
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0336f1646ae77982cbaa886cd2d2ea96
https://doi.org/10.1145/2966986.2967031
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8
High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology
Autor: Kaya Can Akyel, M. Brocard, R. Boumchedda, G. Berhault, O. Billoint, Bastien Giraud, Sebastien Thuries, Edith Beigne, David Turgis, J.-P. Noel
Publikováno v: 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and h
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2118bf62b461a7ec7b1d48603301b37e
https://doi.org/10.1109/s3s.2016.7804376
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9
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications
Autor: F. Giner, D. Noblet, F. Terrier, S. Ibars, Florian Cacho, Sebastien Haendler, Damien Croain, P. Mergault, Nicolas Planes, Franck Arnaud, Christophe Lecocq, M. Parra, Olivier Weber, Alexandre Villaret, David Turgis, R. Ranica, C. Julien, S. Naudet, Lorenzo Ciampolini, V. Huard, M. Quoirin
Publikováno v: VLSI Circuits
Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from −40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bb0eaa26c069f69df3e827ba7f77ce46
https://doi.org/10.1109/vlsic.2016.7573512
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