Zobrazeno 1 - 10
of 43
pro vyhledávání: '"David Selvakumar"'
Autor:
Pranose J Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Dharani Shankar G, Gopal Raut
Publikováno v:
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID).
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9789819900541
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d0f9630beef5e754367837401eb31e0
https://doi.org/10.1007/978-981-99-0055-8_28
https://doi.org/10.1007/978-981-99-0055-8_28
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9789819900541
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f49326043ab877aaf0a7d4e8d681e87e
https://doi.org/10.1007/978-981-99-0055-8_12
https://doi.org/10.1007/978-981-99-0055-8_12
Publikováno v:
2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON).
Publikováno v:
Procedia Computer Science. 171:800-809
RSA (Rivest-Shamir-Adleman) is a widely known and popular public-key cryptosystem used in many security applications. The main mathematical function in RSA is Modular Exponentiation, which is demanding in terms of speed and area. Due to repetitive Mo
Publikováno v:
VDAT
Formal verification and analysis of a crypto hardware requires a formal specification, formal proof of equivalence of the specification with the hardware realization. Pseudo Random Number Generator hardware in Verilog RTL or equivalent has an entropy
Publikováno v:
VDAT
Adoption of large modulus and field sizes for RSA and ECC are of the norm for meeting present day’s security requirements and goals. Modular multiplication (MM) is the key computational unit for both and requires large hardware resources (area) and
Publikováno v:
VDAT
This paper presents a randomized Montgomery Powering Ladder Modular Exponentiation (RMPLME) scheme for side channel attacks (SCA) resistant Rivest-Shamir-Adleman (RSA) and its leakage resilience analysis. This method randomizes the computation time o
Autor:
Shashikala Pattanshetty, Aneesh Raveendran, Annarao Kulkarni, David Selvakumar, Vivian Desalphine, Sandra Jean
Publikováno v:
VLSI Design
Typically verification of arithmetic units is based on simulation/emulation with random / coverage models enabled constrained test vectors or formal techniques. Our PositGen generates coverage models based Posit domain vectors, enabling a native Posi
Publikováno v:
VDAT
A leakage assessment / evaluation and comparative analysis on various architectures of masked AES-128 cryptographic algorithm to mitigate the side channel attack is presented. In this work, unmasked and masked implementations of S-Box for AES-128 at