Zobrazeno 1 - 10
of 16
pro vyhledávání: '"David Michael Bull"'
Publikováno v:
IEEE Journal of Solid-State Circuits
This paper presents a power delivery monitor (PDM) peripheral integrated in a flip-chip packaged 28 nm system-on-chip (SoC) for mobile computing. The PDM is composed entirely of digital standard cells and consists of: 1) a fully integrated VCO-based
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8edac08003f1a78cc9f5f8146e64dad4
https://doi.org/10.1109/jssc.2017.2669025
https://doi.org/10.1109/jssc.2017.2669025
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 15:24-34
Integrated circuits in modern systems-on-chip and microprocessors are typically operated with sufficient timing margins to mitigate the impact of rising process, voltage, and temperature (PVT) variations at advanced process nodes. The widening margin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::253c0499c3d8d0f396f711cebe47c0d8
https://doi.org/10.1109/tdmr.2015.2389038
https://doi.org/10.1109/tdmr.2015.2389038
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:2290-2298
Dynamic adaptation using Razor-based detection and correction of timing errors has demonstrated substantial improvements in performance and energy-efficiency in microprocessors. In this work, we apply Razor to hardware accelerators that find increasi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a15df1499601c6ce74607c031ff98ee
https://doi.org/10.1109/tcsi.2014.2333332
https://doi.org/10.1109/tcsi.2014.2333332
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21:989-999
In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of digital signal processing datapaths without loss of robustness. Timing errors are detected using razor flip-flops on critic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2aba4029e8eaaf1301a4282af5f6e724
https://doi.org/10.1109/tvlsi.2012.2202930
https://doi.org/10.1109/tvlsi.2012.2202930
Autor:
Ganesh Dasika, David Blaauw, Karthik Shivashankar, David Michael Bull, Shidhartha Das, Krisztian Flautner
Publikováno v:
ISSCC
Razor is a hybrid technique for dynamic detection and correction of timing errors. A combination of error detecting circuits and micro-architectural recovery mechanisms creates a system that is robust in the face of timing errors, and can be tuned to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e5fc606ba88a4f4d5e537be4a52b550
https://doi.org/10.1109/jssc.2010.2079410
https://doi.org/10.1109/jssc.2010.2079410
Autor:
Wei-Hsiang Ma, Sanjay Pant, Shidhartha Das, Kevin Lai, David Michael Bull, Carlos Tokunaga, David Blaauw, S. Kalaiselvan
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:32-48
Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a213aa07bfa7104114cd667eca51516
https://doi.org/10.1109/jssc.2008.2007145
https://doi.org/10.1109/jssc.2008.2007145
Publikováno v:
ISLPED
Power delivery is a well-known challenge for high-end microprocessor systems. Comparatively, mobile computing platforms typically consume order-of-magnitude lower currents, but economic and volume constraints limit the quality of the Power Delivery N
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20eea1a630a4062bf5dd23d20e47277b
https://doi.org/10.1109/islped.2015.7273505
https://doi.org/10.1109/islped.2015.7273505
Publikováno v:
VLSIC
A body-coupled symmetric wakeup transceiver is proposed for always-on device discovery in IoT applications requiring security and low-power consumption. The wakeup transceiver (WTRx) is implemented in 65nm CMOS, using digital logic cells and operates
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43deb16d83ac87c28385401d2cd256f6
https://doi.org/10.1109/vlsic.2015.7231338
https://doi.org/10.1109/vlsic.2015.7231338
Publikováno v:
ISSCC
The current trend for System-on-Chip (SoC) compute subsystems is to improve energy efficiency, while operating at a similar power budget as previous generations. Reduced supply voltages and increased transistor density affords SoCs composed of multip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddc77419574d8b6cd0f39204de265dfc
https://doi.org/10.1109/isscc.2015.7063026
https://doi.org/10.1109/isscc.2015.7063026
Publikováno v:
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
Datapath accelerators are a key performance enabler for many digital signal processing systems. Razor provides a means to improve the performance and power efficiency of DSP accelerators by minimizing static guardbands. Unlike with Razor CPU implemen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a388b26e21f291a5bb20be57208acb95
https://doi.org/10.1109/asscc.2013.6690974
https://doi.org/10.1109/asscc.2013.6690974