Zobrazeno 1 - 3
of 3
pro vyhledávání: '"David L. Rude"'
Autor:
Guenter Mayer, Thomas Strach, Yiu-Hing Chan, Gerard M. Salem, Ayan Datta, Doug Malone, David L. Rude, Adam R. Jatkowski, James D. Warnock, Donald W. Plass, Anne E. Gattiker, C-L Kevin Shum, Charles F. Webb, Jeffrey A. Zitz, Aditya Bansal, L. Sigal, Gerald Strevig, Pak-Kin Mak, Howard H. Smith, Ruchir Puri, S. Carey, Hubert Harrer, M. Mayo, Huajun Wen, Yuen Chan
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:9-18
This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4867c44fa93569f4d5652227a4408ac
https://doi.org/10.1109/jssc.2013.2284647
https://doi.org/10.1109/jssc.2013.2284647
Autor:
M. Mayo, Chung-Lung Shum, Huajun Wen, Guenter Mayer, Thomas Strach, D. Malone, Y.-H. Chan, James D. Warnock, S. Carey, L. Sigal, Gerald Strevig, Donald W. Plass, Ruchir Puri, Gerard M. Salem, Anne E. Gattiker, Yiu-Hing Chan, Aditya Bansal, Hubert Harrer, Ayan Datta, Adam R. Jatkowski, Charles F. Webb, Pak-Kin Mak, David L. Rude
Publikováno v:
ISSCC
The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a87f23989edaffc22d46eaac0bad09b4
https://doi.org/10.1109/isscc.2013.6487630
https://doi.org/10.1109/isscc.2013.6487630
Autor:
Brian W. Curran, Y.-H. Chan, S. Carey, Patrick J. Meaney, M. Mayo, L. Sigal, Guenter Mayer, Michael Fee, Lee Evan Eisen, Eric M. Schwarz, Pak-Kin Mak, D. Malone, Frank Malgioglio, Howard H. Smith, T. J. McPherson, Huajun Wen, Thomas Strach, Michael H. Wood, William V. Huott, M. J. Saccamango, James D. Warnock, S. Weitzel, Yuen H. Chan, David L. Rude, R. Averill, Donald W. Plass, Charles F. Webb
Publikováno v:
ISSCC
The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm des
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a548ff33e6ac1c480eb79f9a8031262
https://doi.org/10.1109/isscc.2011.5746223
https://doi.org/10.1109/isscc.2011.5746223